The basic differences between CMOS and TTL logic include CMOS components being more expensive, CMOS circuits not drawing as much power and TTL power consumption increasing more slowly. Other differences include the transmission of digital signals and damage susceptibility.
TTL components are generally less expensive than CMOS components. However, due to smaller chips, CMOS is generally less expensive on the system level. When at rest, CMOS circuits don't draw as much power as TTL circuits. However, higher clock speeds cause CMOS power consumption to increase at a faster rate than TTL. CMOS components are more likely to be damaged from electrostatic discharge than TTL components. Digital signals are more inexpensive and simpler with CMOS chips due to longer rise and fall times.
The power dissipation of CMOS is generally 10 nW per gate while the power dissipation of TTL is typically 10 mW per gate. Propagation delays of TTL are usually 10 nS while propagation delays of CMOS are generally between 25 nS and 50 nS.
The voltage level range for TTL is generally 4.75V - 5.25V. The voltage level range for CMOS ranges from 0 to 1/3 VDD at a low level and 2/3 VDD to VDD at a high level.