Halt synthesiser with an assert?
	Do any Vendors synthesisors actually take action on asserts? I can see it being quite useful, so why dont they do it? for example: .. generic ( word_width : integer; --Only use a multiple of 8 ); .. function check_generics return boolean is begin assert ( (word_width rem 8 ) = 0 ) report "word width must be a multiple of 8"... more » By Tricky  - Nov 18 - 5 new of 5 messages

	DOWNTO versus TO keyword on Component instantiation
	Hello, Does anyone know about the following error in Modelsim ? ** Error: xxx.vhd(2435): (vcom-1012) Slice range direction (to) does not match slice prefix dire ction (downto). The slice range direction on the concerned port are identical on the entity and on the component declaration (DOWNTO keyword) but I cant... more » By pierre0...@gmail.com  - Nov 18 - 2 new of 2 messages

	Aligned PLL clocks in RTL simulation
	Every cloud has a silver lining, but it seems every rose has its thorns too. PLLs/DCMs/DLLs (or whatever your favourite FPGA happens to offer) provide a wonderful way to create multiplied-up clocks within the device. What's more, you can line up the active clock edges so closely that you can treat the x1 and xN clock domains as... more » By Jonathan Bromley  - Nov 17 - 12 new of 12 messages

	Link for Joining the FPGA/CPLD Design Group on LinkedIn
	Link for Joining the FPGA/CPLD Design Group on LinkedIn [link] Group for People Involved In the Design and Verification of FPGA's, other Programmable Logic , and CPLD's to Exchange Idea's and Techniques. You should have FPGA / CPLD Design / Verification on your... more » By cpld-fpga-asic  - Nov 17 - 1 new of 1 message

	testbench
	I wrote a testbench for a 4-bit syn counter. i initialised a 4-bit variable inp ( declared as inout )to 0 and then tried to increment it in a loop as inp=inp + 1; But this statement is creating problems By whereismel...@gmail.com  - Nov 17 - 3 new of 3 messages

Complex testbench design strategy

Hello, I'm now considering the design of a rather complex testbench, and want to consult the dwellers of this list on the best strategy to adopt. The testbench is for a complex multi-functional FPGA. This FPGA has several almost unrelated functions, which it makes sense to check separately. So I'm in doubt as to how to structure my testbench. As I... more » By Eli Bendersky  - Nov 16 - 21 new of 21 messages

	i am trying to use the sd ram of spartan 3 1800a dsp fpta
	i am trying to use the sd ram of spartan 3 1800a dsp fpta would u suggest the method of using the sd ram ofr how i can use the sd ram of my board. By denish  - Nov 15 - 2 new of 2 messages

	near LIBRARY :Syntax error
	I have following code: library IEEE; use IEEE.STD_LOGIC_1164.all; package my_pkg is COMPONENT my_comp PORT( clk : IN STD_LOGIC; a : IN STD_LOGIC; b : OUT STD_LOGIC; c : IN STD_LOGIC; d : INOUT STD_LOGIC; ); END my_comp;... more » By AnandA  - Nov 14 - 2 new of 2 messages

	shift register
	I have written a vhdl code in xilinx for a serial in serial out shift register. It is modelled using 4 d flip flops. The problem is that the output waveform is coming as an undefined signal. [CODE] --D FLIP FLOP FILE entity dff is Port ( d : in STD_LOGIC; clk : in STD_LOGIC; clr : in STD_LOGIC;... more » By coderyogi  - Nov 14 - 7 new of 7 messages

	How portable is this code?
	consider the following functions: function get_i return integer is begin return 10; end function get_i; function get_i return boolean is begin return true; end function get_i; they both have the same name but different return types. are these going to be safe in something like this statement across most, if not... more » By Tricky  - Nov 14 - 4 new of 4 messages