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SDRAM

SDRAM refers to synchronous dynamic random access memory, a term that is used to describe dynamic random access memory that has a synchronous interface. Traditionally, dynamic random access memory (DRAM) has an asynchronous interface which means that it responds as quickly as possible to changes in control inputs. SDRAM has a synchronous interface, meaning that it waits for a clock signal before responding to control inputs and is therefore synchronized with the computer's system bus. The clock is used to drive an internal finite state machine that pipelines incoming instructions. This allows the chip to have a more complex pattern of operation than asynchronous DRAM which does not have a synchronized interface.

Pipelining means that the chip can accept a new instruction before it has finished processing the previous one. In a pipelined write, the write command can be immediately followed by another instruction without waiting for the data to be written to the memory array. In a pipelined read, the requested data appears after a fixed number of clock pulses after the read instruction, cycles during which additional instructions can be sent. (This delay is called the latency and is an important parameter to consider when purchasing SDRAM for a computer.)

SDRAM history

Although the concept of synchronous DRAM has been known since at least the 1970s and was used with early Intel processors, it was only in 1993 that SDRAM began its path to universal acceptance in the electronics industry. In 1993, Samsung introduced its KM48SL2000 synchronous DRAM, and by 2000, SDRAM had replaced virtually all other types of DRAM in modern computers, because of its greater speed.

SDRAM latency is not inherently lower (faster) than asychronous DRAM. Indeed, early SDRAM was somewhat slower than contemporaneous burst EDO DRAM due to the additional logic. The benefits of SDRAM's internal buffering come from its ability to interleave operations to multiple banks of memory, thereby increasing effective bandwidth.

Today, virtually all SDRAM is manufactured in compliance with standards established by JEDEC, an electronics industry association that adopts open standards to facilitate interoperability of electronic components. JEDEC formally adopted its first SDRAM standard in 1993 and subsequently adopted other SDRAM standards, including those for DDR, DDR2 and DDR3 SDRAM.

SDRAM is also available in registered varieties, for systems that require greater scalability such as servers and workstations.

As of 2007, 168-pin SDRAM DIMMs are not used in new PC systems, and 184-pin DDR memory has been mostly superseded. DDR2 SDRAM is the most common type used with new PCs, and DDR3 motherboards and memory are widely available, but more expensive than still-popular DDR2 products.

Today, the world's largest manufacturers of SDRAM include: Samsung Electronics, Micron Technology, Qimonda (formerly Infineon Technologies) and Hynix.

SDRAM timing

There are several limits on DRAM speed. Most noted is the read cycle time, the time between successive read operations to an open row. This time decreased from 10 ns for 100 MHz SDRAM to 5 ns for DDR-400, but has remained relatively unchanged through DDR2-800 and DDR3-1600 generations. However, by operating the interface circuitry at increasingly higher multiples of the fundamental read rate, the achievable bandwidth has increased rapidly.

Another limit is the CAS latency, the time between supplying a column address and receiving the corresponding data. Again, this has remained relatively constant at 10–15 ns through that last few generations of DDR SDRAM.

In operation, CAS latency is a specific number of clock cycles programmed into the SDRAM's mode register and expected by the DRAM controller. Any value may be programmed, but the SDRAM will not operate correctly if it is too low. At higher clock rates, the useful CAS latency in clock cycles naturally increases. 10–15 ns is 2–3 cycles (CL2–3) of the 200 MHz clock of DDR-400 SDRAM, CL4-6 for DDR2-800, and CL8-12 for DDR3-1600. Slower clock cycles will naturally allow lower numbers of CAS latency cycles.

SDRAM modules have their own timing specifications, which may be slower than those of the chips on the module. When 100 MHz SDRAM chips first appeared, some manufacturers sold "100 MHz" modules that could not reliably operate at that speed. In response, Intel published the PC100 standard, which outlines requirements and guidelines for producing a memory module that can operate reliably at 100 MHz. This standard was widely influential, and the term "PC100" quickly became a common identifier for 100 MHz SDRAM modules, and modules are now commonly designated with "PC"-prefixed numbers (although the actual meaning of the numbers has changed).

SDR SDRAM

Originally simply known as "SDRAM", Single Data Rate SDRAM can accept one command and transfer one word of data per clock cycle. Typical clock frequencies are 100 and 133 MHz. Chips are made with a variety of data bus sizes (most commonly 4, 8 or 16 bits), but chips are generally assembled into 168-pin DIMMs that read or write 64 (non-ECC) or 72 (ECC) bits at a time.

Use of the data bus is intricate and requires a complex DRAM controller. This is because data written to the DRAM must be presented in the same cycle as a write command, but reads produce output 2 or 3 cycles after the read command. The DRAM controller must ensure that the data bus is never required for a read and a write at the same time.

Typical SDR SDRAM clock speeds are 66, 100, and 133 MHz (15, 10, and 7.5 ns/cycle). Speeds up to 150 MHz were available for overclockers.

SDRAM control signals

All commands are timed relative to the rising edge of a clock signal. In addition to the clock, there are 6 control signals, mostly active low, which are sampled on the rising edge of the clock:

  • CKE Clock Enable. When this signal is low, the chip behaves as if the clock has stopped. No commands are interpreted and command latency times do not elapse. The state of other control lines is not relevant. The effect of this signal is actually delayed by one clock cycle. That is, the current clock cycle proceeds as usual, but the following clock cycle is ignored, except for testing the CKE input again. Normal operations resume on the rising edge of the clock after the one where CKE is sampled high.
    Put another way, all other chip operations are timed relative to the rising edge of a masked clock. The masked clock is the logical AND of the input clock and the state of the CKE signal during the previous rising edge of the input clock.
  • /CS Chip Select. When this signal is high, the chip ignores all other inputs (except for CKE), and acts as if a NOP command is received.
  • DQM Data Mask. (The letter Q appears because, following digital logic conventions, the data lines are known as "DQ" lines.) When high, these signals suppress data I/O. When accompanying write data, the data is not actually written to the DRAM. When asserted high two cycles before a read cycle, the read data is not output from the chip. There is one DQM line per 8 bits on a x16 memory chip or DIMM.
  • /RAS Row Address Strobe. Despite the name, this is not a strobe, but rather simply a command bit. Along with /CAS and /WE, this selects one of 8 commands.
  • /CAS Column Address Strobe. Despite the name, this is not a strobe, but rather simply a command bit. Along with /RAS and /WE, this selects one of 8 commands.
  • /WE Write enable. Along with /RAS and /CAS, this selects one of 8 commands. This generally distinguishes read-like commands from write-like commands.

SDRAM devices are internally divided into 2 or 4 independent internal data banks. One or two bank address inputs (BA0 and BA1) select which bank a command is directed toward.

Many commands also use an address presented on the address input pins. Some commands, which either do not use an address, or present a column address, also use A10 to select variants.

The commands understood are as follows.

/CS /RAS /CAS /WE BAn A10 An Command
H x x x x x x Command inhibit (No operation)
L H H H x x x No operation
L H H L x x x Burst Terminate: stop a burst read or burst write in progress.
L H L H bank L column Read: Read a burst of data from the currently active row.
L H L H bank H column Read with auto precharge: As above, and precharge (close row) when done.
L H L L bank L column Write: Write a burst of data to the currently active row.
L H L L bank H column Write with auto precharge: As above, and precharge (close row) when done.
L L H H bank row Active (activate): open a row for Read and Write commands.
L L H L bank L x Precharge: Deactivate current row of selected bank.
L L H L x H x Precharge all: Deactivate current row of all banks.
L L L H x x x Auto refresh: Refresh one row of each bank, using an internal counter. All banks must be precharged.
L L L L 0 0 mode Load mode register: A0 through A9 are loaded to configure the DRAM chip.
The most significant settings are CAS latency (2 or 3 cycles) and burst length (1, 2, 4 or 8 cycles)

SDRAM operation

A 512 megabyte (i.e., 512 MiB) SDRAM DIMM might be made of 8 or 9 SDRAM chips, each containing 512 Mbit (512 Mibit) of storage, and each one contributing 8 bits to the DIMM's 64- or 72-bit width.

A typical 512 Mbit SDRAM chip internally contains 4 independent 16 Mbyte banks. Each bank is an array of 8192 rows of 16384 bits each. A bank is either idle, active, or changing from one to the other.

An active command activates an idle bank. It takes a 2-bit bank address (BA0–BA1) and a 13-bit row address (A0–A12), and reads that row into the bank's array of 16384 sense amplifiers. This is also known as "opening" the row. This operation has the side effect of refreshing that row.

Once the row has been activated or "opened", read and write commands are possible. Each command requires a column address, but because each chip works on 8 bits at a time, there are 2048 possible column addresses, needing only 11 address lines (A0–A9,A11). Activation requires a minimum time, called the row-to-column delay, or tRCD. This time, rounded up to the next multiple of the clock period, specifies the minimum number of cycles between an active command, and a read or write command. During these delay cycles, arbitrary commands may be sent to other banks; they are completely independent.

When a read command is issued, the SDRAM will produce the corresponding output data on the DQ lines in time for the rising edge of the clock 2 or 3 cycles later (depending on the configured CAS latency). Subsequent words of the burst will be produced in time for subsequent rising clock edges.

A write command is accompanied by the data to be written on the DQ lines during the same rising edge. It is the duty of the memory controller to ensure that the SDRAM is not driving read data on the DQ lines at the same time that it needs to drive write data on those lines. This can be done by waiting until a read burst is not in progress, terminating the read burst, or using the DQM control line.

When the memory controller wants to access a different row, it must first return that bank's sense amplifiers to an idle state, ready to sense the next row. This is known as a "precharge" operation, or "closing" the row. A precharge may be commanded explicitly, or it may be performed automatically at the conclusion of a read or write operation. Again, there is a minimum time, the row precharge delay, tRP, which must elapse before that bank is fully idle and it may receive another active command.

Although refreshing a row is an automatic side effect of activating it, there is a minimum time for this to happen, which requires a minimum row access time tRAS, that must elapse between an active command opening a row, and the corresponding precharge command closing it. This limit is usually dwarfed by desired read and write commands to the row, so its value has little effect on typical performance.

Command interactions

The no operation command is always permitted.

The load mode register command requires that all banks be idle, and a delay afterward for the changes to take effect.

The auto refresh command also requires that all banks be idle, and takes a refresh cycle time tRFC to return the chip to the idle state. (This time is usually equal to tRCD+tRP.)

The only other command that is permitted on an idle bank is the active command. This takes, as mentioned above, tRCD before the row is fully open and can accept read and write commands.

When a bank is open, there are four commands permitted: read, write, burst terminate, and precharge. Read and write commands begin bursts, which can be interrupted by following commands.

Interrupting a read burst

A read, burst terminate, or precharge command may be issued at any time after a read command, and will interrupt the read burst after the configured CAS latency. So if a read command is issued on cycle 0, another read command is issued on cycle 2, and the CAS latency is 3, then the first read command will begin bursting data out during cycles 3 and 4, then the results from the second read command will appear beginning with cycle 5.

If the command issued on cycle 2 were burst terminate, or a precharge of the active bank, then no output would be generated during cycle 5.

Although the interrupting read may be to any active bank, a precharge command will only interrupt the read burst if it is to the same bank or all banks; a precharge command to a different bank will not interrupt a read burst.

To interrupt a read burst by a write command is possible, but more difficult. It can be done, if the DQM signal is used to suppress output from the SDRAM so that the memory controller may drive data over the DQ lines to the SDRAM in time for the write operation. Because the effects of DQM on read data are delayed by 2 cycles, but the effects of DQM on write data are immediate, DQM must be raised (to mask the read data) beginning at least two cycles before write command, but must be lowered for the cycle of the write command (assuming you want the write command to have an effect).

Doing this in only two clock cycles requires careful coordination between the time the SDRAM takes to turn off its output a clock edge and the time the data must be supplied as input to the SDRAM for the write on the following clock edge. If the clock frequency is too high to allow sufficient time, three cycles may be required.

If the read command includes auto-precharge, the precharge begins the same cycle as the

Interrupting a write burst

Any read, write, or burst terminate command, to any bank, will terminate a write burst immediately; the data supplied on the DQ lines when the second command is issued will only be used if the second command is also a write.

It is possible to terminate a write burst with a precharge command (to the same bank), but it is also more difficult. There is a minimum write time, tWR, that must elapse between the last write operation to a bank (the last unmasked cycle of a write burst) and a following precharge command, so a write burst may only be terminated by a precharge command if enough trailing cycles are masked (using DQM) to make up the necessary tWR. A write-with-auto-precharge command includes this delay automatically.

Interrupting an auto-precharge command

Handling interruption of reads and writes with auto precharge is an optional SDRAM feature, but many do support it. If this is used, the precharge (after a read) or tWR wait followed by precharge (after a read) begins the same cycle as the interrupting command.

SDRAM burst ordering

A modern microprocessor with a cache will generally access memory in units of cache lines. To transfer a 64-byte cache line requires 8 consecutive accesses to a 64-bit DIMM, which can all be triggered by a single read or write command by configuring the SDRAM chips, using the mode register, to perform 8-word bursts.

A cache line fetch is typically triggered by a read from a particular address, and SDRAM allows the "critical word" of the cache line to be transferred first. ("Word" here refers to the width of the SDRAM chip or DIMM, which is 64 bits for a typical DIMM.) SDRAM chips support two possible conventions for the ordering of the remaining words in the cache line.

Bursts always access an aligned block of BL consecutive words beginning on a multiple of BL. So, for example, a 4-word burst access to any column address from 4 to 7 will return words 4–7. The ordering, however, depends on the requested address, and the configured burst type option: sequential or interleaved. Typically, a memory controller will require one or the other.

When the burst length is 1 or 2, the burst type does not matter. For a burst length of 1, the requested word is the only word accessed. For a burst length of 2, the requested word is accessed first, and the other word in the aligned block is accessed second. This is the following word if an even address was specified, and the previous word if an odd address was specified.

For the sequential burst mode, later words are accessed in increasing address order, wrapping back to the start of the block when the end is reached. So, for example, for a burst length of 4, and a requested column address of 5, the words would be accessed in the order 5-6-7-4. If the burst length were 8, the access order would be 5-6-7-0-1-2-3-4. This is done by adding a counter to the column address, and ignoring carries past the burst length.

The interleaved burst mode computes the address using an exclusive or operation between the counter and the address. Using the same starting address of 5, a 4-word burst would return words in the order 5-4-7-6. An 8-word burst would be 5-4-7-6-1-0-3-2. Although more confusing to humans, this can be easier to implement in hardware, and is preferred by Intel microprocessors.

If the requested column address is at the start of a block, both burst modes return data in the same sequential sequence. The difference only matters if fetching a cache line from memory in critical-word-first order.

SDRAM mode register

Single data rate SDRAM has a single 10-bit programmable mode register. Later double-data-rate SDRAM standards add additional mode registers, addressed using the bank address pins. For SDR SDRAM, the bank address pins and address lines A10 and above are ignored, but should be zero during a mode register write.

The bits are M9 through M0, presented on address lines A9 through A0 during a load mode register cycle.

  • M9: Write burst mode. If 0, writes use the read burst length and mode. If 1, all writes are non-burst (single location).
  • M8, M7: Operating mode. Reserved, and must be 00.
  • M6, M5, M4: CAS latency. Only 010 (CL2) and 011 (CL3) are legal. Specifies the number of cycles between a read command and data output from the chip. The chip has a fundamental limit on this value in nanoseconds; during initialization, the memory controller must use its knowledge of the clock frequency to translate that limit into cycles.
  • M3: Burst type. - requests sequential burst ordering, while 1 requests interleaved burst ordering.
  • M2, M1, M0: Burst length. Values of 000, 001, 010 and 011 specify a burst size of 1, 2, 4 or 8 words, respectively. Each read (and write, if M9 is 0) will perform that many accesses, unless interrupted by a burst stop or other command. A value of 111 specifies a full-row burst. The burst will continue until interrupted. Full-row bursts are only permitted with the sequential burst type

Auto refresh

It is possible to refresh a RAM chip by opening and closing (activating and precharging) each row in each bank. However, to simplify the memory controller, SDRAM chips support an "auto refresh" command, which performs these operations to one row in each bank simultaneously. The SDRAM also maintains an internal counter, which iterates over all possible rows. The memory controller must simply issue a sufficient number of auto refresh commands (one per row, 4096 in the example we have been using) every refresh interval (tREF = 64 ms is a common value). All banks must be idle (closed, precharged) when this command is issued.

Low power modes

As mentioned, the clock enable (CKE) input can be used to effectively stop the clock to an SDRAM. The CKE input is sampled each rising edge of the clock, and if it is low, the following rising edge of the clock is ignored for all purposes other than checking CKE.

If CKE is lowered while the SDRAM is performing operations, it simple "freezes" in place until CKE is raised again.

If the SDRAM is idle (all banks precharged, no commands in progress) when CKE is lowered, the SDRAM automatically enters power-down mode, consuming minimal power until CKE is raised again. This must not last longer than the maximum refresh interval tREF, or memory contents may be lost. It is legal to stop the clock entirely during this time for additional power savings.

Finally, if CKE is lowered at the same time as an auto-refresh command is sent to the SDRAM, the SDRAM enters self-refresh mode. This is like power down, but the SDRAM uses an on-chip timer to generate internal refresh cycles as necessary. The clock may be stopped during this time. While self-refresh mode consumes slightly more power than power-down mode, it allows the memory controller to be disabled entirely, which commonly more than makes up the difference.

DDR SDRAM

While the access latency of DRAM is fundamentally limited by the DRAM array, DRAM has very high potential bandwidth because each internal read is actually a row of many thousands of bits. To make more of this bandwidth available to users, a Double Data Rate interface was developed. This uses the same commands, accepted once per cycle, but reads or writes two words of data per clock cycle. Some minor changes to the SDR interface timing were made in hindsight, and the supply voltage was reduced from 3.3 to 2.5 V.

DDR SDRAM (sometimes called "DDR1" for greater clarity) doubles the minimum read or write unit; every access refers to at least two consecutive words.

Typical DDR SDRAM clock speeds are 133, 166 and 200 MHz (7.5, 6, and 5 ns/cycle), generally described as DDR-266, DDR-333 and DDR-400 (3.75, 3, and 2.5 ns per beat). Corresponding 184-pin DIMMS are known as PC2100, PC2700 and PC3200. Speeds up to DDR-550 (PC4400) are available for a price.

DDR2 SDRAM

DDR2 SDRAM is very similar to DDR SDRAM, but doubles the minimum read or write unit again, to 4 consecutive words. The bus protocol was also simplified to allow higher speed operation. (In particular, the "burst terminate" command is deleted.) This allows the bus speed of the SDRAM to be doubled without increasing the speed of internal RAM operations; instead, internal operations are performed in units 4 times as wide as SDRAM. Also, an extra bank address pin (BA2) was added to allow 8 banks on large RAM chips.

Typical DDR2 SDRAM clock speeds are 200, 266, 333 or 400 MHz (5, 3.75, 3 and 2.5 ns/cycle), generally described as DDR2-400, DDR2-533, DDR2-667 and DDR2-800 (2.5, 1.875, 1.5 and 1.25 ns per beat). Corresponding 240-pin DIMMS are known as PC2-3200 through PC2-6400. DDR2 SDRAM is now available at a clock speed of 533 MHz generally described as DDR2-1066 and the corresponding DIMMS are known as PC-8500 (also named PC-8600 depending on the manufacturer). Speeds up to DDR2-1250 (PC2-10000) are available for a price.

Note that because internal operations are at 1/2 the clock rate, DDR2-400 memory (internal clock speed 100 MHz) has somewhat higher latency than DDR-400 (internal clock speed 200 MHz).

DDR3 SDRAM

DDR3 continues the trend, doubling the minimum read or write unit to 8 consecutive words. This allows another doubling of bandwidth and external bus speed without having to change the speed of internal operations, just the width.

DDR3 memory chips are being made commercially , and computer systems are available that use them as of the second half of 2007 , with expected significant usage in 2008.. Initial speeds were 400 and 533 MHz, which would be described as DDR3-800 and DDR3-1066, but 667 and 800 MHz (DDR3-1333 and DDR3-1600) are now common and speeds up to DDR3-1800 are available for a premium.

DDR4 SDRAM

DDR4 SDRAM will be the successor to DDR3 SDRAM. It was revealed at the Intel Developer Forum in San Francisco and is currently in the design state and is expected to be released in 2012.

The new chips are expected to run at 1.2 volts or less, versus the 1.5 volts of DDR3 chips and have in excess of 2 billion data transfers per second.

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