Most early PC motherboards (8088-based PCs and XTs) used socketed DIP chips. With the introduction of 286-based PC/ATs, which could use larger amounts of memory, memory modules evolved to save motherboard space and to ease memory expansion. Instead of plugging in eight or nine single DIP DRAM chips, only one additional memory module was needed to increase the memory of the computer. A few 286-based computers used (often non-standard) memory modules like SIPP memory (single in-line pin package). The SIPP's 30 pins often bent or broke during installation, which is why they were quickly replaced by SIMMs which used contact plates rather than pins.
SIMMs were invented and patented by Wang Laboratories. One of Wang's scientists, James Clayton, invented what was to become the basic memory module, now known as a SIMM (single in-line memory module) in 1983. The first SIMMs appeared on the PS/2 in the mid 1980s, having been first proposed by Skip Coppola while at IBM. They solved several problems at the time, including shrinking motherboard real estate (they took up much less board space than socketed chips) as well as the effects of rapidly advancing memory capacities (a motherboard would quickly become obsolete based on its sockets for a particular RAM chip capacity) This also allowed the manufacturer (IBM at this time) to source RAM chips from different vendors and in different packaging, yet still allow them to be interchangeable through this intermediate form (the SIMM).
The first variant of SIMMs has 30 pins and provides 8 bits of data (9 bits in parity versions). They were used in 286, 386 and 486 systems.
The second variant of SIMMs has 72 pins and provides 32 bits of data (36 bits in parity versions). These appeared on 486, Pentium, Pentium Pro and even some Pentium II systems. By the mid 90s, 72-pin SIMMs had replaced 30-pin SIMMs.
Non-IBM PC computers such as UNIX workstations may use proprietary non-standard SIMMs. The Macintosh IIfx use proprietary non-standard SIMMs with 64 pins.
DRAM technologies used in SIMMs include EDO and FPM.
Due to the differing data bus widths of the memory modules and some processors, sometimes several modules must be installed in identical pairs or in identical groups of four to fill a memory bank. The general rule of thumb is a 286 or 386SX system (data bus width of 16 bits) would require two 30-pin SIMMs for a memory bank. On 386DX or 486 systems (data bus width of 32 bits), either four 30-pin SIMMs or one 72-pin SIMM are required for one memory bank. On Pentium systems (data bus width of 64 bits), two 72-pin SIMMs are required. However, some Pentium systems have support for a "half bank mode", in which the data bus would be shortened to only 32-bits to allow operation of a single SIMM. Conversely, some 386 and 486 systems use what is known as "memory interleaving", which requires twice as many SIMMs and effectively doubles the bandwidth.
The earliest SIMM sockets were conventional push-type sockets. These were soon replaced by ZIF sockets in which the SIMM was inserted and rotated until it locked into place. To install a SIMM, the module must be placed in the socket at an angle, then rotated (angled) into position. To remove one, the two metal or plastic clips at each end must be pulled to the side, then the SIMM must be tilted back and pulled out. The earlier sockets used plastic retainer clips which were found to break, so steel clips replaced them.
72-pin SIMM: 1 MB, 2 MB, 4 MB, 8 MB, 16 MB, 32 MB, 64 MB, 128 MB, 256 MB
| Pin # | Nomenclature | Signal Description |
|---|---|---|
| 1 | VCC | +5VDC |
| 2 | CAS | Column Address Strobe |
| 3 | DQ1 | Data 0 |
| 4 | A0 | Address 0 |
| 5 | A1 | Address 1 |
| 6 | DQ2 | Data 1 |
| 7 | A2 | Address 2 |
| 8 | A3 | Address 3 |
| 9 | VSS | Ground |
| 10 | DQ3 | Data 2 |
| 11 | A4 | Address 4 |
| 12 | A5 | Address 5 |
| 13 | DQ4 | Data 3 |
| 14 | A6 | Address 6 |
| 15 | A7 | Address 7 |
| 16 | DQ5 | Data 4 |
| 17 | A8 | Address 8 |
| 18 | A9 | Address 9 |
| 19 | A10 | Address 10 |
| 20 | DQ6 | Data 5 |
| 21 | W | Write Enable |
| 22 | VSS | Ground |
| 23 | DQ7 | Data 6 |
| 24 | NC | No Internal Connection |
| 25 | DQ8 | Data 7 |
| 26 | NC | No Internal Connection |
| 27 | RAS | Row Address Strobe |
| 28 | NC | No Internal Connection |
| 29 | NC | No Internal Connection |
| 30 | VCC | +5VDC |
| Pin # | Non-Parity | Parity | Signal Description |
|---|---|---|---|
| 1 | VSS | VSS | Ground |
| 2 | DQ0 | DQ0 | Data 0 |
| 3 | DQ1 | DQ1 | Data 1 |
| 4 | DQ2 | DQ2 | Data 2 |
| 5 | DQ3 | DQ3 | Data 3 |
| 6 | DQ4 | DQ4 | Data 4 |
| 7 | DQ5 | DQ5 | Data 5 |
| 8 | DQ6 | DQ6 | Data 6 |
| 9 | DQ7 | DQ7 | Data 7 |
| 10 | VCC | VCC | +5 VDC |
| 11 | PD1 | PD1 | Presence Detect 1 |
| 12 | A0 | A0 | Address 0 |
| 13 | A1 | A1 | Address 1 |
| 14 | A2 | A2 | Address 2 |
| 15 | A3 | A3 | Address 3 |
| 16 | A4 | A4 | Address 4 |
| 17 | A5 | A5 | Address 5 |
| 18 | A6 | A6 | Address 6 |
| 19 | A10 | A10 | Address 10 |
| 20 | n/c | PQ8 | Data 8 (Parity 1) |
| 21 | DQ9 | DQ9 | Data 9 |
| 22 | DQ10 | DQ10 | Data 10 |
| 23 | DQ11 | DQ11 | Data 11 |
| 24 | DQ12 | DQ12 | Data 12 |
| 25 | DQ13 | DQ13 | Data 13 |
| 26 | DQ14 | DQ14 | Data 14 |
| 27 | DQ15 | DQ15 | Data 15 |
| 28 | A7 | A7 | Address 7 |
| 29 | A11 | A11 | Address 11 |
| 30 | VCC | VCC | +5 VDC |
| 31 | A8 | A8 | Address 8 |
| 32 | A9 | A9 | Address 9 |
| 33 | /RAS3 | RAS3 | Row Address Strobe 3 |
| 34 | /RAS2 | RAS2 | Row Address Strobe 2 |
| 35 | DQ16 | DQ16 | Data 16 |
| 36 | n/c | PQ17 | Data 17 (Parity 2) |
| 37 | DQ18 | DQ18 | Data 18 |
| 38 | DQ19 | DQ19 | Data 19 |
| 39 | VSS | VSS | Ground |
| 40 | /CAS0 | CAS0 | Column Address Strobe 0 |
| 41 | /CAS2 | CAS2 | Column Address Strobe 2 |
| 42 | /CAS3 | CAS3 | Column Address Strobe 3 |
| 43 | /CAS1 | CAS1 | Column Address Strobe 1 |
| 44 | /RAS0 | RAS0 | Row Address Strobe 0 |
| 45 | /RAS1 | RAS1 | Row Address Strobe 1 |
| 46 | A12 | A12 | Address 12 |
| 47 | /WE | WE | Read/Write |
| 48 | A13 | A13 | Address 13 |
| 49 | DQ20 | DQ20 | Data 20 |
| 50 | DQ21 | DQ21 | Data 21 |
| 51 | DQ22 | DQ22 | Data 22 |
| 52 | DQ23 | DQ23 | Data 23 |
| 53 | DQ24 | DQ24 | Data 24 |
| 54 | DQ25 | DQ25 | Data 25 |
| 55 | n/c | PQ26 | Data 26 (Parity 3) |
| 56 | DQ27 | DQ27 | Data 27 |
| 57 | DQ28 | DQ28 | Data 28 |
| 58 | DQ29 | DQ29 | Data 29 |
| 59 | DQ31 | DQ31 | Data 31 |
| 60 | DQ30 | DQ30 | Data 30 |
| 61 | VCC | VCC | +5 VDC |
| 62 | DQ32 | DQ32 | Data 32 |
| 63 | DQ33 | DQ33 | Data 33 |
| 64 | DQ34 | DQ34 | Data 34 |
| 65 | n/c | PQ35 | Data 35 (Parity 4) |
| 66 | PD2 | PD2 | Presence Detect 2 |
| 67 | PD3 | PD3 | Presence Detect 3 |
| 68 | PD4 | PD4 | Presence Detect 4 |
| 69 | PD5 | PD5 | Presence Detect 5 |
| 70 | PD6 | PD6 | Presence Detect 6 |
| 71 | PD7 | PD7 | Presence Detect 7 |
| 72 | VSS | VSS | Ground |