RapidIO was developed by Mercury Computer Systems and Motorola (now Freescale), primarily as an upgraded interconnect for Mercury's embedded NUMA/cluster ("multicomputer") signal processing computers.
There are two incarnations of RapidIO Technology: Parallel RapidIO and Serial RapidIO. The main difference between the two is that Parallel RapidIO has a separate clock signal, while Serial RapidIO uses 8B/10B encoding to transmit the clock along with the signal serially.
Packets are big-endian, 256 bytes, with 8-bit or 16-bit addresses, and routed by crossbar switches. Links are point-to-point, with handshaking and reservations to ensure that packets need not be dropped. Links are commonly half-duplex parallel Low voltage differential signaling or serial fiber optic. Special signaling allows timestamps to flood fill through the fabric without concern for packet boundaries. RapidIO is designed to support memory mapping, mailbox queues, and doorbell-style interrupts.
Rapid IO interfaces can be driven at different baud rates. The maximum speed achieved can be 6.25 Gbit/s per lane.