The EDGE ISA is defined using the operations in a single block and facilitates encoding the data dependencies within the instruction itself to relieve the processor of detecting dependencies. The data dependencies are then used to model a dataflow graph (or a data graph) which is used as the abstraction used to express concurrency. Though EDGE ISAs make each instruction more expensive, the cost is ammortized as instruction block contains a large number of instructions (the reference TRIPS implementation uses a 1024-instruction window).
EDGE ISA works on a block-atomic model, i.e., a block of instructions is an atomic unit of execution. All the processor cores which form the execution blocks are named in the ISA and blocks are mapped to them. A block of instructions does not have control statements, but can have predicated instructions. The dataflow graph is encoded using these blocks, by specifying the flow of data from one block of instructions to another, or to some storage area. Each block can individually be a sequential program or a SIMD program.
New server processor speeds things up; University group targets industrial, consumer and scientific computing applications.(University of Texas at Austin's TRIPS (Tera-op, Reliable, Intelligently adaptive Processing System))
Apr 24, 2007; Byline: Michael Cooney The prototype of a innovative general-purpose computer processor, which has the potential of reaching...