Explicit Data Graph Execution or EDGE is an instruction set architecture which takes a different path from the traditional instruction / register designs like RISC and CISC. Instead, EDGE processors map the computations required in a basic block, called operands, to a flexible reconfigurable routing layer, allowing the individual operations to communicate their results to the consuming operations without going through the bottleneck of a register file. Each block is calculated in parallel in a different core, which may either be a self-sustained generic processor or an application-specific processor.

The EDGE ISA is defined using the operations in a single block and facilitates encoding the data dependencies within the instruction itself to relieve the processor of detecting dependencies. The data dependencies are then used to model a dataflow graph (or a data graph) which is used as the abstraction used to express concurrency. Though EDGE ISAs make each instruction more expensive, the cost is ammortized as instruction block contains a large number of instructions (the reference TRIPS implementation uses a 1024-instruction window).

EDGE ISA works on a block-atomic model, i.e., a block of instructions is an atomic unit of execution. All the processor cores which form the execution blocks are named in the ISA and blocks are mapped to them. A block of instructions does not have control statements, but can have predicated instructions. The dataflow graph is encoded using these blocks, by specifying the flow of data from one block of instructions to another, or to some storage area. Each block can individually be a sequential program or a SIMD program.

External links

• Overview of the TRIPS project An implementation of an EDGE architecture.