Diagram convention
Most timing diagrams use the following conventions:- Higher value is a logic one
- Lower value is a logic zero
- A slot showing a high and low is an either or (such as on a data line)
- A Z indicates high impedance
- A greyed out slot is a don't-care or indeterminate
SPI
The timing diagram on the right describes the Serial Peripheral Interface Bus (SPI). Most SPI master nodes have the ability to set the clock polarity (CPOL) and clock phase (CPHA) with respect to the data. This timing diagram shows the clock for both values of CPOL as well as the values for the two data lines (MISO & MOSI) for each value of CPHA. Note that when CPHA=1 then the data is delayed by one-half clock cycle.
SPI operates in the following way:
- The master determines an appropriate CPOL & CPHA value
- The master pulls down the slave select (SS) line for a specific slave chip
- The master clocks SCK at a specific frequency
- During each of the 8 clock cycles the transfer is full duplex:
- The master writes on the MOSI line and reads the MISO line
- The slave writes on the MISO line and reads the MOSI line
- When finished the master can continue with another byte transfer or pull SS high to end the transfer
When a slave's SS line is high then both of its MISO and MOSI line should be high impedance so to avoid disrupting a transfer to a different slave. Prior to SS being pulled low, the MISO & MOSI lines are indicated with a "z" for high impedance. Also prior to the SS being pulled low the "cycle #" row is meaningless and is shown greyed-out.
Note that for when CPHA=1 the MISO & MOSI lines are undefined and are also shown greyed-out.
A more typical timing diagram has just a single clock and numerous data lines
This article is licensed under the GNU Free Documentation License.
Last updated on Monday August 18, 2008 at 12:34:57 PDT (GMT -0700)
View this article at Wikipedia.org - Edit this article at Wikipedia.org - Donate to the Wikimedia Foundation
Diagram convention
Most timing diagrams use the following conventions:- Higher value is a logic one
- Lower value is a logic zero
- A slot showing a high and low is an either or (such as on a data line)
- A Z indicates high impedance
- A greyed out slot is a don't-care or indeterminate
SPI
The timing diagram on the right describes the Serial Peripheral Interface Bus (SPI). Most SPI master nodes have the ability to set the clock polarity (CPOL) and clock phase (CPHA) with respect to the data. This timing diagram shows the clock for both values of CPOL as well as the values for the two data lines (MISO & MOSI) for each value of CPHA. Note that when CPHA=1 then the data is delayed by one-half clock cycle.
SPI operates in the following way:
- The master determines an appropriate CPOL & CPHA value
- The master pulls down the slave select (SS) line for a specific slave chip
- The master clocks SCK at a specific frequency
- During each of the 8 clock cycles the transfer is full duplex:
- The master writes on the MOSI line and reads the MISO line
- The slave writes on the MISO line and reads the MOSI line
- When finished the master can continue with another byte transfer or pull SS high to end the transfer
When a slave's SS line is high then both of its MISO and MOSI line should be high impedance so to avoid disrupting a transfer to a different slave. Prior to SS being pulled low, the MISO & MOSI lines are indicated with a "z" for high impedance. Also prior to the SS being pulled low the "cycle #" row is meaningless and is shown greyed-out.
Note that for when CPHA=1 the MISO & MOSI lines are undefined and are also shown greyed-out.
A more typical timing diagram has just a single clock and numerous data lines
This article is licensed under the GNU Free Documentation License.
Last updated on Monday August 18, 2008 at 12:34:57 PDT (GMT -0700)
View this article at Wikipedia.org - Edit this article at Wikipedia.org - Donate to the Wikimedia Foundation
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