The chip integrates 128 channels with low-noise charge-sensitive preamplifiers and shapers. The pulse shape can be chosen such that it complies with LHCb specifications: a peaking time of 25ns with a remainder of the peak voltage after 25ns of less than 30%. A comparator per channel with configurable polarity provides a binary signal. Four adjacent comparator channels are being ORed and brought off chip via LVDS drivers. Either the shaper or comparator output is sampled with the LHC bunch-crossing frequency of 40MHz into an analogue pipeline. This ring buffer has a programmable latency of max. 160 sampling intervals and an integrated derandomising buffer of 16 stages. For analogue readout data is multiplexed with up to 40MHz onto 1 or 4 ports. A binary readout mode operates at up to 80MHz output rate on two ports. Current drivers bring the serialised data off chip. The chip can accept trigger rates up to 1.1MHz to perform a dead-timeless readout within 900ns per trigger. For testability and calibration purposes, a charge injector with adjustable pulse height is implemented. The bias settings and various other parameters can be controlled via a standard I²C-interface. The chip is radiation hardened to an accumulated dose of more than 100Mrad. Robustness against Single Event Upset is achieved by redundant logic.