Technical details
The K5 was based upon an internal highly parallel 29k RISC processor architecture with an x86 decoding front-end. The K5 offered good x86 compatibility. All models had 4.3 million transistors, with five integer units that could process instructions out of order and one floating point unit. The branch target buffer was four times the size of the Pentium's and register renaming improved parallel performance of the pipelines. The chips speculative execution of instructions reduced pipeline stall. It touted an instruction cache of 16 KiB, which was double that of the Pentium. Further, the primary cache was a "4-way" set associative, instead of the Pentium's "2-way" set. The K5 lacked MMX instructions, which Intel started offering in its Pentium MMX processors that were launched in early 1997. Compared to the Pentium the K5's floating point unit had around 10% less performance clock for clock.
Performance
The K5 project represented an early chance for AMD to take technical leadership from Intel. Although the chip addressed the right design concepts, the actual engineering implementation had its issues. The low clock rates were, in part, due to AMD's limitations as a "cutting edge" manufacturing company at the time, in part due to the design itself (many levels of logic, thus slowing it down). Having a branch prediction unit four times the size of the Pentium, yet reportedly not delivering superior performance is an example of how the actual implementation fell short of the projects goals. Additionally, while the K5's floating point performance was better than that of the Cyrix 6x86, it was weaker than that of the Pentium. Because it was late to market and did not meet performance expectations, the K5 never gained the acceptance among large computer manufacturers that the Am486 and AMD K6 enjoyed.Models
There were two sets of K5 processors, internally called the SSA/5 and the 5k86, both released with the K5 label. The "SSA/5" line ran from 75 to 100 MHz (5K86 P75 to P100, later K5 PR-75 to PR100); the "5k86" line ran from 90 to 133 MHz. However, AMD used what it called a PR rating, or performance rating, to label the chips according to their equivalence to a Pentium of that clock speed. Thus, a 116 MHz chip from the second line was marketed as the "K5 PR166". Manufacturing delays caused the PR200's arrival to unfortunately nearly align with the release of K6. Since AMD did not want the two chips competing, the K5-PR200 only arrived in small numbers. Enthusiasts have speculated that many PR200 chips were sold as PR166, because of easy overclocking with later PR166 chips.SSA/5
- Sold as 5K86 P75 to P100, later as K5 PR75 to PR100
- 4.3 million Transistors in 500 or 350 nm
- L1-Cache: 8 + 16 KiB (Data + Instructions)
- Socket 5 and Socket 7
- VCore: 3.52V
- Front side bus: 50 (PR75), 60 (PR90), 66 MHz (PR100)
- First release: March 27, 1996
- Clockrate: 75, 90, 100 MHz
5k86
- Sold as K5 PR120 to PR166 (PR200)
- 4.3 million Transistors in 350 nm
- L1-Cache: 8 + 16 KiB (Data + Instructions)
- Socket 5 and Socket 7
- VCore: 3.52V
- Front side bus: 60 (PR120/150), 66 MHz
- First release: October 7, 1996
- Clockrate: 90 (PR120), 100 (PR133), 105 (PR150), 116.6 (PR166), 133 MHz (PR200)
References
External links
- AMD: AMD-K5 Processor Overview
- Technical overview of the K5 series
- Pictures of K5 chips at CPUShack.com
- The AMD K5, a much underrated chip
- AMD K5 technical specifications
This article is licensed under the GNU Free Documentation License.
Last updated on Monday June 16, 2008 at 05:15:21 PDT (GMT -0700)
View this article at Wikipedia.org - Edit this article at Wikipedia.org - Donate to the Wikimedia Foundation
Technical details
The K5 was based upon an internal highly parallel 29k RISC processor architecture with an x86 decoding front-end. The K5 offered good x86 compatibility. All models had 4.3 million transistors, with five integer units that could process instructions out of order and one floating point unit. The branch target buffer was four times the size of the Pentium's and register renaming improved parallel performance of the pipelines. The chips speculative execution of instructions reduced pipeline stall. It touted an instruction cache of 16 KiB, which was double that of the Pentium. Further, the primary cache was a "4-way" set associative, instead of the Pentium's "2-way" set. The K5 lacked MMX instructions, which Intel started offering in its Pentium MMX processors that were launched in early 1997. Compared to the Pentium the K5's floating point unit had around 10% less performance clock for clock.
Performance
The K5 project represented an early chance for AMD to take technical leadership from Intel. Although the chip addressed the right design concepts, the actual engineering implementation had its issues. The low clock rates were, in part, due to AMD's limitations as a "cutting edge" manufacturing company at the time, in part due to the design itself (many levels of logic, thus slowing it down). Having a branch prediction unit four times the size of the Pentium, yet reportedly not delivering superior performance is an example of how the actual implementation fell short of the projects goals. Additionally, while the K5's floating point performance was better than that of the Cyrix 6x86, it was weaker than that of the Pentium. Because it was late to market and did not meet performance expectations, the K5 never gained the acceptance among large computer manufacturers that the Am486 and AMD K6 enjoyed.Models
There were two sets of K5 processors, internally called the SSA/5 and the 5k86, both released with the K5 label. The "SSA/5" line ran from 75 to 100 MHz (5K86 P75 to P100, later K5 PR-75 to PR100); the "5k86" line ran from 90 to 133 MHz. However, AMD used what it called a PR rating, or performance rating, to label the chips according to their equivalence to a Pentium of that clock speed. Thus, a 116 MHz chip from the second line was marketed as the "K5 PR166". Manufacturing delays caused the PR200's arrival to unfortunately nearly align with the release of K6. Since AMD did not want the two chips competing, the K5-PR200 only arrived in small numbers. Enthusiasts have speculated that many PR200 chips were sold as PR166, because of easy overclocking with later PR166 chips.SSA/5
- Sold as 5K86 P75 to P100, later as K5 PR75 to PR100
- 4.3 million Transistors in 500 or 350 nm
- L1-Cache: 8 + 16 KiB (Data + Instructions)
- Socket 5 and Socket 7
- VCore: 3.52V
- Front side bus: 50 (PR75), 60 (PR90), 66 MHz (PR100)
- First release: March 27, 1996
- Clockrate: 75, 90, 100 MHz
5k86
- Sold as K5 PR120 to PR166 (PR200)
- 4.3 million Transistors in 350 nm
- L1-Cache: 8 + 16 KiB (Data + Instructions)
- Socket 5 and Socket 7
- VCore: 3.52V
- Front side bus: 60 (PR120/150), 66 MHz
- First release: October 7, 1996
- Clockrate: 90 (PR120), 100 (PR133), 105 (PR150), 116.6 (PR166), 133 MHz (PR200)
References
External links
- AMD: AMD-K5 Processor Overview
- Technical overview of the K5 series
- Pictures of K5 chips at CPUShack.com
- The AMD K5, a much underrated chip
- AMD K5 technical specifications
This article is licensed under the GNU Free Documentation License.
Last updated on Monday June 16, 2008 at 05:15:21 PDT (GMT -0700)
View this article at Wikipedia.org - Edit this article at Wikipedia.org - Donate to the Wikimedia Foundation
Copyright © 2008, Dictionary.com, LLC. All rights reserved.