A Stuck-at fault
is a particular fault model
used by fault simulators and Automatic test pattern generation
(ATPG) tools to mimic a manufacturing defect within an integrated circuit
. Individual signals and pins are assumed to be stuck
at Logical '1', '0' and 'X'. For example, an output is tied to a logical 1 state during test generation to assure that a manufacturing defect with that type of behavior can be found with a specific test pattern. Likewise the output could be tied to a logical 0 to model the behavior of a defective circuit that cannot switch its output pin.
Not all faults can be analyzed using the Stuck-at fault model. Compensation for static hazards, namely branching signals, can render a circuit untestable using this model.