The first short-term goal is to implement a prototype PCI graphics card dubbed OGD1 using a field-programmable gate array (FPGA) chip. Although this card will not be able to compete with existing graphics cards on the market performance- or functionality-wise, it will be useful as a tool for prototyping the first application-specific integrated circuit (ASIC) board, as well as for other professionals needing programmable graphics cards or FPGA-based prototyping boards. It is hoped that this prototype will attract enough interest to gain some profit and attract investors for the next card, since it is expected to cost around $2,000,000 to start the production of a specialized ASIC design. Later AGP and PCI Express variations will follow. The initial prototypes of OGD1 are available as of January 2007.
Full specifications will be published and open source device drivers will be released. All RTL will be released. Source code to the device drivers and BIOS will be released under the MIT and BSD licenses. The RTL (in Verilog) used for the FPGA and the RTL used for the ASIC are planned to be released under the GNU General Public License (GPL).
It will have 256 MiB of DDR RAM, passively cooled and follow the DDC, EDID, DPMS and VBE VESA standards. TV-out is also planned.
Versioning schema for OGD1 will go like this:
{Root Number} – {Video Memory}{Video Output Interfaces}{Special Options e.g: A1 OGA firmware installed}
| Field | Example Value | Example Description |
|---|---|---|
| Root number | OGD1P- | OGD1 board with PCI Bus |
| Video memory | 256 | 256 MiB |
| Video outputs, in order, skip any not installed | ||
| First interface | D | Dual-link DVI |
| Second interface | D | Dual-link DVI |
| Third interface | A | Analog video, 75 ohm, VGA compatible |
| Fourth interface | V | TV video |
| Special options, in alphanumeric order, each preceded by a dash | ||
| Factory firmware-RTL | A1 | OGA1 Firmware |
Main components of OGD1 graphics card (shown on the picture)