DDR SDRAM (double data rate synchronous dynamic random access memory) is a class of memory integrated circuit used in computers. It achieves nearly twice the bandwidth of the preceding [single data rate] SDRAM by double pumping (transferring data on the rising and falling edges of the clock signal) without increasing the clock frequency.

With data being transferred 64 bits at a time, DDR SDRAM gives a transfer rate of (memory bus clock rate) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a bus frequency of 100 MHz, DDR SDRAM gives a maximum transfer rate of 1600 MB/s.

JEDEC has set standards for speeds of DDR SDRAM, divided into two parts: The first specification is for memory chips and the second is for memory modules. As DDR-SDRAM is superseded by the newer DDR2 SDRAM, the older version is sometimes referred to as DDR1-SDRAM.

Specification standards

Chips and modules

Standard name Memory clock Cycle time I/O Bus clock Data transfers per second JEDEC standard VDDQ voltage Module name Peak transfer rate
DDR-200 100 MHz 10 ns 100 MHz 200 Million 2.5v +/- 0.2v PC-1600 1600MB/s
DDR-266 133 MHz 7.5 ns 133 MHz 266 Million 2.5v +/- 0.2v PC-2100 2100 MB/s
DDR-300 150 MHz 6.67 ns 150 MHz 300 Million Not a JEDEC standard PC-2400 2400 MB/s
DDR-333 166 MHz 6 ns 166 MHz 333 Million 2.5v +/- 0.2v PC-2700 2700 MB/s
DDR-400 200 MHz 5 ns 200 MHz 400 Million 2.6v +/- 0.1v PC-3200 3200 MB/s

Note: All above listed (except DDR-300) are specified by JEDEC as JESD79.. All RAM speeds in-between or above these listed specifications are not standardized by JEDEC — most often they are simply manufacturer optimizations using higher-tolerance or overvolted chips.

The package sizes in which DDR SDRAM is manufactured are also standardized by JEDEC.

There is no architectural difference between DDR SDRAM designed for different clock frequencies, e.g. PC-1600 (designed to run at 100 MHz) and PC-2100 (designed to run at 133 MHz). The number simply designates the speed that the chip is guaranteed to run at, hence DDR SDRAM can be run at either lower or higher clock speeds than those for which it was made. These practices are known as underclocking and overclocking respectively.

DDR SDRAM for desktop computers DIMMs have 184 pins (as opposed to 168 pins on SDRAM, or 240 pins on DDR2 SDRAM), and can be differentiated from SDRAM DIMMs by the number of notches (DDR SDRAM has one, SDRAM has two). DDR for notebook computers SO-DIMMs have 200 pins which is the same number of pins as DDR2 SO-DIMMs. These two specifications are notched very similarly and care must be taken during insertion when you are unsure of a correct match. DDR SDRAM operates at a voltage of 2.5 V, compared to 3.3 V for SDRAM. This can significantly reduce power usage. Chips and modules with DDR-400/PC-3200 standard have a nominal voltage of 2.6 Volt.

Many new chipsets use these memory types in dual-channel configurations, which doubles or quadruples the effective bandwidth.

Chip characteristics

  • DRAM density. Size of the chip in megabits. Example: 256 Mbit — 32 MB chip.
  • DRAM organization. Written in the form of 64M x 4, where 64M is a number of storage units (64 million), x4 (pronounced «by 4») — number of bits per chip, which equals the number of bits per storage unit. There are x4, x8, and x16 DDR chips. The x4 chips allow the use of advanced error correction features like Chipkill, memory scrubbing and Intel SDDC, while the x8 and x16 chips are somewhat more expensive.

Module characteristics

  • Capacity
  • # of DRAM Devices. The number of chips is a multiple of 8 for non-ECC modules and a multiple of 9 for ECC modules. Chips can occupy one side (Single Sided) or both sides (Dual Sided) of the module. The maximum amount of chips per DDR module is 36 (9x4).
  • # of DRAM ranks (also known as rows or sides). Any given module can have 1, 2 or 4 ranks, but only 1 rank of a module can be active at any moment of time. When a module has two or more ranks, the memory controller must periodically switch between them by performing close and open operations. Do not confuse rows in this context with rows used to describe internal chip architecture (that is why the term rank is to be preferred). The term sides is also confusing because it incorrectly suggests that this is tied to the physical placement of chips on the module.
  • Timings: CAS Latency (CL), Clock Cycle Time (tCK), Row Cycle Time (tRC), Refresh Row Cycle Time (tRFC), Row Active Time (tRAS).
  • Buffering: Registered vs. unbuffered
  • packaging: typically DIMM or SO-DIMM
  • power consumption: increases with speed

Module and chip characteristics are inherently linked.

Total module capacity is a product of one chip's capacity by the number of chips. ECC modules multiply it by 8/9 because they use one bit per byte for error correction. A module of any particular size can therefore be assembled either from 32 small chips (36 for ECC memory), or 16(18) or 8(9) bigger ones.

DDR memory bus width per channel is 64 bits (72 for ECC memory). Total module bit width is a product of bits per chip by number of chips. It also equals number of ranks (rows) multiplied by DDR memory bus width. Consequently a module with greater amount of chips or using x8 chips instead of x4 will have more ranks.

Example: Variations of 1 GB PC2100 Registered DDR SDRAM module with ECC
Module size Number of chips Chip size Chip organization Number of rows (ranks)
1 GB 36 256 Mbit 64M x 4 2
1 GB 18 512 Mbit 64M x 8 2
1 GB 18 512 Mbit 128M x 4 1

This example compares different real-world server memory modules with a common size of 1 GB. One should definitely be careful buying 1 GB memory modules, because all these variations can be sold under one price position without stating whether they are x4 or x8, single or dual ranked.

There is a common belief that number of module rows or ranks equals number of sides. As above data shows, this is not true. One can find (2-side, 1-rank) or (2-side, 4-rank) modules. One can even think of 1-side, 2-rank memory module having 16(18) chips on single side x8 each, but it's unlikely such a module was ever produced.

High Density vs. Low Density

In this context High Density memory means non-ECC 184 pin SDRAM memory.


PC3200 is DDR SDRAM specified to operate at 200 MHz using DDR-400 chips with a bandwidth of 3,200 MB/s. As DDR stands for Double Data Rate this means that the effective clock rate of PC3200 memory is 400 MHz.

1 GB PC3200 non-ECC modules are usually made with 16 512 Mb chips, 8 down each side (512 Mb x 16) / (8 bits per Byte) = 1024 MB. The individual chips making up a 1 GB memory module are usually organised with 64M bits and a data width of 8 bits, commonly expressed as 64M x 8. Memory manufactured in this way is LOW DENSITY RAM and will usually be OK with any motherboard specifying PC3200 DDR-400 memory.

High Density RAM

In the context of the 1 GB non-ECC PC3200 SDRAM module there is very little visually to differentiate Low Density from High Density RAM. High Density DDR RAM modules will, like their Low Density counterparts, usually be double sided with eight 512 Mb chips per side. The difference is that each chip, instead of being organised in a 64M x 8 configuration is organised with 128M bits and a data width of 4 bits, or 128M x 4. To further confuse the issue, some RAM is labelled as 128M x 8, and is also called high density.

Most High Density PC3200 modules are assembled using Samsung chips. These chips come in both the familiar 22 x 10mm (approx) TSOP2 and smaller squarer 12 x 9mm (approx) FBGA package sizes. High density Samsung chips can be identified by the numbers on each chip. If the sixth and seventh characters are "04" (for example K4H510438D-UCCC) then the chips are x 4 and High Density. If the sixth and seventh characters are "08" then the chips are x 8 and Low Density.

High Density RAM devices were designed to be used in registered memory modules for servers. As a result, Performance or response times may suffer when used on a desktop or workstation. JEDEC standards do not apply to high-density DDR RAM in desktop implementations. JEDEC's technical documentation however supports 128Mb X 4Mb semiconductors as such that contradicts 128X4 being classified as high density. As such "High Density" is a relative term which can be used to describe memory which is not supported by a particular motherboard's memory controller.


DDR (DDR1) has been superseded by DDR2 SDRAM, which has some modifications to allow higher clock frequency, but operates on the same principle as DDR. Competing with DDR2 are Rambus XDR DRAM. DDR2 has become the standard, as XDR is lacking support. DDR3 SDRAM is a new standard that offers even faster performance and new features.

DDR's prefetch buffer depth is 2 bits; DDR2 uses 4 bits. Although the effective clock speeds of DDR2 are higher than for DDR, the overall performance was no greater in the early implementations, primarily due to the high latencies of the first DDR2 modules. DDR2 started to be effective by the end of 2004, as modules with lower latencies became available.

Memory manufacturers have stated that it is impractical to mass-produce DDR1 memory with effective clock rates in excess of 400 MHz. DDR2 picks up where DDR1 leaves off, and is available at clock rates of 400 MHz and higher.

RDRAM is a particularly expensive alternative to DDR SDRAM, and most manufacturers have dropped its support from their chipsets.


MDDR is an acronym that some enterprises use for Mobile DDR SDRAM, a type of memory used in some portable electronic devices, like mobile phones, handhelds, and digital audio players. While standard DDR SDRAM operates at a voltage of 2.5 V, MDDR operates at voltage of 1.8 V, which allows a reduced power consumption.


See also

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