Time-Triggered Protocol


TTP (Time-Triggered Protocol) is an open and modular control system platform technology that supports the design of upgradeable, reusable and easy-to-integrate systems. As a time-triggered field bus, it can significantly impact the design of modern electronics and control system architectures for next-generation vehicles and industrial applications.

TTP was originally designed at the Vienna University of Technology in the early 80s. From 1998 onwards TTTech Computertechnik AG has taken over the further development of TTP, providing software and hardware solutions for this data communication protocol. Today TTP communication controller chips and IP are available from multiple sources including austriamicrosystems (SWX: AMS), ON Semiconductor (NASDAQ: ONNN) and ALTERA (NasdaqGM: ALTR).


TTP is a dual-channel 25 Mbit/s time-triggered field bus. It can operate using one or both channels with maximum bandwidth of 2x 25 Mbit/s. With replicated data on both channels, redundant communication is supported.

As a fault-tolerant time-triggered protocol, TTP provides autonomous fault-tolerant message transport at known times and with minimal jitter by employing a TDMA (Time-Division Multiple Access) strategy on replicated communication channels. TTP offers fault-tolerant clock synchronization that establishes the global time base without relying on a central time server.

TTP provides a membership service to inform every correct node about the consistency of data transmission. This mechanism can be viewed as a distributed acknowledgment service that informs the application promptly if an error in the communication system has occurred. If state consistency is lost, the application is notified immediately.

Additionally, TTP includes the service of clique avoidance to detect faults outside the fault hypothesis, which cannot be tolerated at the protocol level.

Technical Details

Frame, Message, Slot, TDMA Round and Cluster Cycle

Data communication in TTP is organized in TDMA rounds. A TDMA round is divided into slots. Each node in the communication system has one slot – its sending slot – and must send frames in every round. The frame size allocated to a node can vary from 2 to 240 bytes in length, each frame usually carrying several messages. The cluster cycle is a recurring sequence of TDMA rounds; in different rounds different messages can be transmitted in the frames, but in each cluster cycle the complete set of state messages is repeated. The data is protected by a 24-bit CRC (Cyclic Redundancy Check). The schedule is stored in the MEDL (Message Descriptor List) within the communication controller. The figure below gives a better understanding of those technical terms.

Clock synchronization

The clock synchronization is necessary to provide all nodes with an equivalent time concept. Each node measures the difference between the a priori known expected and the observed arrival time of a correct message to learn about the difference between the sender’s clock and the receiver’s clock. A fault-tolerant average algorithm needs this information to periodically calculate a correction term for the local clock so that the clock is kept in synchrony with all other clocks of the cluster.

Membership and Acknowledgment

A major philosophy in the design of TTP is that the protocol should transmit data consistently to all correct nodes of the distributed system and that, in case of a failure, the communication system should decide on its own which node is faulty. These properties are achieved by the membership protocol and an acknowledgment mechanism.

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