Static random access memory (SRAM) is a type of semiconductor memory where the word static indicates that, unlike dynamic RAM (DRAM), it does not need to be periodically refreshed, as SRAM uses bistable latching circuitry to store each bit. SRAM exhibits data remanence, but is still volatile in the conventional sense that data is eventually lost when the memory is not powered.
The term SDRAM, which stands for synchronous DRAM, should not be confused with SRAM.
Random access means that locations in the memory can be written to or read from in any order, regardless of the memory location that was last accessed.
Each bit in an SRAM is stored on four transistors that form two cross-coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. Two additional access transistors serve to control the access to a storage cell during read and write operations.
A typical SRAM uses six MOSFETs to store each memory bit.
In addition to such 6T SRAM, other kinds of SRAM chips use 8T, 10T, or more transistors per bit -- sometimes to implement more ports in a register file.
Generally, the fewer transistors needed per cell, the smaller each cell can be. Since the cost of processing a silicon wafer is relatively fixed, using smaller cells and so packing more bits on one wafer reduces the cost per bit of memory.
Memory cells that use fewer than 6 transistors are possible — but such 3T or 1T cells are DRAM, not SRAM (even 1T-SRAM).
Access to the cell is enabled by the word line (WL in figure) which controls the two access transistors M5 and M6 which, in turn, control whether the cell should be connected to the bit lines: BL and BL. They are used to transfer data for both read and write operations. Although it is not strictly necessary to have two bit lines, both the signal and its inverse are typically provided in order to improve noise margins.
During read accesses, the bit lines are actively driven high and low by the inverters in the SRAM cell. This improves SRAM speed compared to DRAMs—in a DRAM, the bit line is connected to storage capacitors and charge sharing causes the bitline to swing upwards or downwards. The symmetric structure of SRAMs also allows for differential signalling, which makes small voltage swings more easily detectable. Another difference with DRAM that contributes to making SRAM faster is that commercial chips accept all address bits at a time. By comparison, commodity DRAMs have the address multiplexed in two halves, i.e. higher bits followed by lower bits, over the same package pins in order to keep their size and cost down.
The size of an SRAM with m address lines and n data lines is 2m words, or 2m × n bits.
An SRAM cell has three different states it can be in: standby where the circuit is idle, reading when the data has been requested and writing when updating the contents. The three different states work as follows:
If the word line is not asserted, the access transistors M5 and M6 disconnect the cell from the bit lines. The two cross coupled inverters formed by M1 – M4 will continue to reinforce each other as long as they are disconnected from the outside world.
Assume that the content of the memory is a 1, stored at Q. The read cycle is started by precharging both the bit lines to a logical 1, then asserting the word line WL, enabling both the access transistors. The second step occurs when the values stored in Q and Q are transferred to the bit lines by leaving BL at its precharged value and discharging BL through M1 and M5 to a logical 0. On the BL side, the transistors M4 and M6 pull the bit line toward VDD, a logical 1. If the content of the memory was a 0, the opposite would happen and BL would be pulled toward 1 and BL toward 0.
The start of a write cycle begins by applying the value to be written to the bit lines. If we wish to write a 0, we would apply a 0 to the bit lines, i.e. setting BL to 1 and BL to 0. This is similar to applying a reset pulse to a SR-latch, which causes the flip flop to change state. A 1 is written by inverting the values of the bit lines. WL is then asserted and the value that is to be stored is latched in. Note that the reason this works is that the bit line input-drivers are designed to be much stronger than the relatively weak transistors in the cell itself, so that they can easily override the previous state of the cross-coupled inverters. Careful sizing of the transistors in an SRAM cell is needed to ensure proper operation.
A RAM memory with an access time of 70 ns will output valid data within 70 ns from the time that the address lines are valid. But the data will remain for a hold time as well (5-10 ns). Rise and fall times also influence valid timeslots with approximately ~5 ns
. By reading the lower part of an address range bits in sequence (page cycle) one can read with significantly shorter access time (30 ns).
It is also referred to as Shadow Random Access Memory
Applications and Uses
SRAM is a little more expensive, but faster and significantly less power hungry (especially idle) than DRAM
. It is therefore used where either speed or low power, or both, are principal considerations. SRAM is also easier to control (interface to) and generally more truly random access
than modern types of DRAM. Due to a more complex internal structure, SRAM is less dense than DRAM and is therefore not used for high-capacity, low-cost applications such as the main memory
in personal computers
Clock speed and power
consumption of SRAM varies widely depending on how frequently it is accessed; it can
be as power-hungry as dynamic RAM, when used at high frequencies, and some ICs
can consume many watts
at full speed. On the other hand, static RAM used at a somewhat slower pace, such as in applications with moderately clocked microprocessors, draw very little power and can have a nearly negligible power consumption when sitting idle — in the region of a few microwatts.
Static RAM exists primarily as:
- general purpose products
- with asynchronous interface, such as the 28 pin 32Kx8 chips (usually named XXC256), and similar products up to 16 Mbit per chip
- with synchronous interface, usually used for caches and other applications requiring burst transfers, up to 18 Mbit (256Kx72) per chip
- integrated on chip
- as RAM or cache memory in microcontrollers (usually from around 32 bytes up to 128 kilobytes)
- as the primary caches in powerful microprocessors, such as the x86 family, and many others (from 8 kB, up to several megabytes)
- to store the registers and parts of the state-machines used in some microprocessors -- see register file
- on application specific ICs, or ASICs (usually in the order of kilobytes)
- in FPGAs and CPLDs (usually in the order of a few kilobytes or less)
Many categories of industrial and scientific subsystems, automotive electronics, and similar, contains static RAM. Some amounts (kilobytes or less) is also embedded in practically all modern appliances, toys, etc that implements an electronic user interface. Several megabytes may be used in complex products such as digital cameras, cell phones, synthesizers, etc.
SRAM in its dual-ported form is sometimes used for realtime digital signal processing circuits.
SRAM is also used in personal computers, workstations, routers and peripheral equipment: internal CPU caches
and external burst mode
SRAM caches, hard disk
buffers, etc. LCD screens
also normally employ static RAM to hold the image displayed (or to be printed). Small SRAM buffers are also found in CDROM
drives; usually 256 kB or more are used to buffer track data, which is transferred in blocks instead of as single values. The same applies to cable modems
and similar equipment connected to computers.
Hobbyists often prefer SRAM due to the ease of interfacing. It is much easier to work with than DRAM
as there are no refresh cycles and the address and data buses are directly accessible rather than multiplexed. In addition to buses and power connections, SRAM usually require only three controls: Chip Enable (CE), Write Enable (WE) and Output Enable (OE).
Types of SRAM
By transistor type
- Asynchronous — independent of clock frequency; data in and data out are controlled by address transition
- Synchronous — all timings are initiated by the clock edge(s). Address, data in and other control signals are associated with the clock signals
- ZBT (ZBT stands for zero bus turnaround) — the turnaround is the number of clock cycles it takes to change access to the SRAM from write to read and vice versa. The turnaround for ZBT SRAMs or the latency between read and write cycle is zero.
- syncBurst (syncBurst SRAM or synchronous-burst SRAM) — features synchronous burst write access to the SRAM to speed up write operation to the SRAM.
- DDR SRAM — Synchronous, single read/write port, double data rate IO
- Quad Data Rate SRAM — Synchronous, separate read & write ports, double data rate IO
- Digital Integrated Circuits - a design perspective. J. M. Rabaey, A. Chandrakasan, B. Nikolić. Prentice Hall, 2003. ISBN 0-13-120764-4.