Bit-Serial Digital Architecture

Introduction

In digital logic applications, Bit-Serial architectures are direct contrast to Bit-Parallel where a data word tends to be a one to one function of the system clock signal. A Bit-Serial architecture processes a data word as a function of the system clock signal multiplied by the length of the data word. Hence, only one bit of data is processed in a given component at a given point in time.

References

Below are referenced some examples of research making use of Bit-Serial endowed architectures.

Application of FPGA technology to accelerate the finite-difference time-domain (FDTD) method

BIT-Serial FIR Filters with CSD Coefficients for FPGAs