A two's-complement system or two's-complement arithmetic is a system in which negative numbers are represented by the two's complement of the absolute value; this system is the most common method of representing signed integers on computers. In such a system, a number is negated (converted from positive to negative or vice versa) by computing its two's complement. An N-bit two's-complement numeral system can represent every integer in the range −2N-1 to +2N-1-1.
The two's-complement system has the advantage of not requiring that the addition and subtraction circuitry examine the signs of the operands to determine whether to add or subtract. This property makes the system both simpler to implement and capable of easily handling higher precision arithmetic. Also, zero has only a single representation, obviating the subtleties associated with negative zero, which exists in ones'-complement systems.
The method of complements can also be applied in base-10 arithmetic, using ten's complements by analogy with two's complements.
Fundamentally, the system represents negative integers by counting backward and wrapping around. The boundary between positive and negative numbers is arbitrary, but the de facto rule is that all negative numbers have a left-most bit (most significant bit) of one. Therefore, the most positive 4-bit number is 0111 (7) and the most negative is 1000 (−8). Because of the use of the left-most bit as the sign bit, the absolute value of the most negative number (|−8| = 8) is too large to represent. For example, an 8-bit number can only represent every integer from −128 to 127 (2^(8−1) = 128) inclusive. Negating a two's complement number is simple: Invert all the bits and add one to the result. For example, negating 1111, we get 0000 + 1 = 1. Therefore, 1111 must represent −1.
The system is useful in simplifying the implementation of arithmetic on computer hardware. Adding 0011 (3) to 1111 (−1) at first seems to give the incorrect answer of 10010. However, the hardware can simply ignore the left-most bit to give the correct answer of 0010 (2). Overflow checks still must exist to catch operations such as summing 0100 and 0100.
The system therefore allows addition of negative operands without a subtraction circuit and a circuit that detects the sign of a number. Moreover, that addition circuit can also perform subtraction by taking the two's complement of a number (see below), which only requires an additional cycle or its own adder circuit. Lastly, the two's complement system allows a subtraction circuit to return 1001, equivalent to −0001, for 0001 − 0010 rather than 1111. To perform the former, the circuit merely pretends an extra left-most bit of 1 exists. To perform the latter, there must be a sign check, a possible rearrangement of the number, and finally a subtraction.
In two's complement notation, a positive number is represented by its ordinary binary representation, using enough bits that the high bit, the sign bit, is 0. The two's complement operation is the negation operation, so negative numbers are represented by the two's complement of the representation of the absolute value.
In finding the two's complement of a binary number, the bits are inverted, or "flipped", by using the bitwise NOT operation; the value of 1 is then added to the resulting value. Bit overflow is ignored, which is the normal case with zero.
For example, beginning with the signed 8-bit binary representation of the decimal value 5, using subscripts to indicate the base of a representation needed to interpret its value:
The most significant bit is 0, so the pattern represents a non-negative (positive) value. To convert to −5 in two's-complement notation, the bits are inverted; 0 becomes 1, and 1 becomes 0:
At this point, the numeral is the ones' complement of the decimal value 5. To obtain the two's complement, 1 is added to the result, giving:
The result is a signed binary number representing the decimal value −5 in two's-complement form. The most significant bit is 1, so the value represented is negative.
The two's complement of a negative number is the corresponding positive value. For example, inverting the bits of −5 (above) gives:
And adding one gives the final value:
The value of a two's-complement binary number can be calculated by adding up the power-of-two weights of the "one" bits, but with a negative weight for the most significant (sign) bit; for example:
Note that the two's complement of zero is zero: inverting gives all ones, and adding one changes the ones back to zeros (the overflow is ignored). Also the two's complement of the most negative number representable (e.g. a one as the sign bit and all other bits zero) is itself. Hence, there appears to be an 'extra' negative number.
A more formal definition of a two's-complement negative number (denoted by N* in this example) is derived from the equation , where N is the corresponding positive number and n is the number of bits in the representation.
For example, to find the 4 bit representation of -5:
The calculation can be done entirely in base 10, converting to base 2 at the end:
In computer circuitry, this method is no faster than the "complement and add one" method; both methods require working sequentially from right to left, propagating logic changes. The method of complementing and adding one can be sped up by a standard carry look-ahead adder circuit; the alternative method can be sped up by a similar logic transformation.
|Decimal||4-bit two's complement||8-bit two's complement|
When turning a two's-complement number with a certain number of bits into one with more bits (e.g., when copying from a 1 byte variable to a two byte variable), the sign bit must be repeated in all the extra bits and lower bits.
Some processors have instructions to do this in a single instruction. On other processors a conditional must be used followed with code to set the relevant bits or bytes.
Similarly, when a two's-complement number is shifted to the right, the sign bit must be maintained. However when shifted to the left, a 0 is shifted in. These rules preserve the common semantics that left shifts multiply the number by two and right shifts divide the number by two.
Both shifting and doubling the precision are important for some multiplication algorithms. Note that unlike addition and subtraction, precision extension and right shifting are done differently for signed vs unsigned numbers.
|invert bits||0111 1111|
|add one||1000 0000|
The two's complement of the minimum number in the range will not have the desired effect of negating the number. For example, the two's complement of −128 in an 8-bit system results in the same binary number. This is because a positive value of 128 cannot be represented with an 8-bit signed binary numeral. Note that this is detected as an overflow condition since there was a carry into but not out of the sign bit. This can lead to unexpected bugs in that a naive implementation of absolute value could return a negative number.
Although the number is an exception, it is a valid number in regular two's complement systems. All arithmetic operations work with it both as an operand and (unless there was an overflow) a result.
If the classes are taken to represent the numbers 0 to 2n − 1, and overflow ignored, then these are the unsigned integers. But each of these numbers is equivalent to itself minus 2n. So the classes could be understood to represent −2n−1 to 2n−1 − 1, by subtracting 2n from half of them (specifically [2n−1, 2n−1]).
For example, with eight bits, the unsigned bytes are 0 to 255. Subtracting 256 from the top half (128 to 255) yields the signed bytes −128 to 127.
The relationship to two's complement is realised by noting that 256 = 255 + 1, and (255 − x) is the ones' complement of x.
Example −95 modulo 256 is equivalent to 161 since
1111 1111 255
− 0101 1111 − 95
1010 0000 (ones' complement) 160
+ 1 + 1
1010 0001 (two's complement) 161
11111 111 (carry)
0000 1111 (15)
+ 1111 1011 (-5)
0000 1010 (10)
This process depends upon restricting to 8 bits of precision; a carry to the (nonexistent) 9th most significant bit is ignored, resulting in the arithmetically correct result of 10.
The last two bits of the carry row (reading right-to-left) contain vital information: whether the calculation resulted in an arithmetic overflow, a number too large for the binary system to represent (in this case greater than 8 bits). An overflow condition exists when a carry (an extra 1) is generated into but not out of the far left sign bit, or out of but not into the sign bit. As mentioned above, the sign bit is the leftmost bit of the result.
In other terms, if the last two carry bits (the ones on the far left of the top row in these examples) are both 1's or both 0's, the result is valid; if the last two carry bits are "1 0" or "0 1", a sign overflow has occurred. Conveniently, an XOR operation on these two bits can quickly determine if an overflow condition exists. As an example, consider the 4-bit addition of 7 and 3:
+ 0011 (3)
1010 (−6) invalid!
In this case, the far left two (MSB) carry bits are "01", which means there was a two's-complement addition overflow. That is, ten is outside the permitted range of −8 to 7.
In general, any two n-bit numbers may be added without overflow, by first sign-extending both of them to n+1 bits, and then adding as above. The n+1 bit result is large enough to represent any possible sum (e.g. 5 bits can represent values in the range −16 to 15) so overflow will never occur. It is then possible, if desired, to 'truncate' the result back to n bits; the value is preserved if and only if the discarded bit is a proper sign extension of the retained result bits. This provides another method of detecting overflow — which is equivalent to the method of comparing the carry bits — but which may be easier to implement in some situations, since it does not require access to the internals of the addition.
11110 000 (borrow)
0000 1111 (15)
− 1111 1011 (−5)
0001 0100 (20)
Overflow is detected the same way as for addition, by examining the two leftmost (most significant) bits of the borrows; overflow has occurred if they are different.
Another example is a subtraction operation where the result is negative: 15 − 35 = −20:
11100 000 (borrow)
0000 1111 (15)
− 0010 0011 (35)
1110 1100 (−20)
As for addition, overflow in subtraction may be avoided (or detected after the operation) by first sign-extending both inputs by an extra bit.
× 11111011 (-5)
This is very inefficient; by doubling the precision ahead of time, all additions must be double-precision and at least twice as many partial products are needed than for the more efficient algorithms actually implemented in computers. Some multiplication algorithms are designed for two's complement, notably Booth's multiplication algorithm. Methods for multiplying sign-magnitude numbers don't work with two's-complement numbers without adaptation. There isn't usually a problem when the multiplicand (the one being repeatedly added to form the product) is negative; the issue is setting the initial bits of the product correctly when the multiplier is negative. Two methods for adapting algorithms to handle two's-complement numbers are common:
As an example of the second method, take the common add-and-shift algorithm for multiplication. Instead of shifting partial products to the left as is done with pencil and paper, the accumulated product is shifted right, into a second register that will eventually hold the least significant half of the product. Since the least significant bits are not changed once they are calculated, the additions can be single precision, accumulating in the register that will eventually hold the most significant half of the product. In the following example, again multiplying 6 by −5, the two registers and the extended sign bit are separated by "|":
0 0110 (6) (multiplicant with extended sign bit)
× 1011 (-5) (multiplier)
0|0110|0000 (first partial product (rightmost bit is 1))
0|0011|0000 (shift right, preserving extended sign bit)
0|1001|0000 (add second partial product (next bit is 1))
0|0100|1000 (shift right, preserving extended sign bit)
0|0100|1000 (add third partial product: 0 so no change)
0|0010|0100 (shift right, preserving extended sign bit)
1|1100|0100 (subtract last partial product since it's from sign bit)
1|1110|0010 (shift right, preserving extended sign bit)
|1110|0010 (discard extended sign bit, giving the final answer, -30)
Gosper's end conclusion is not necessarily meant to be taken seriously, and it is akin to a mathematical joke. The critical step is "", i.e., "". This presupposes a method by which an infinite string of 1's is considered a number, which requires an extension of the finite place-value concepts in elementary arithmetic. It is meaningful either as part of a two's-complement notation for all integers, as a typical 2-adic number, or even as one of the generalized sums defined for the divergent series of real numbers 1 + 2 + 4 + 8 + · · ·.