In wave motion, the fraction of the time required to complete a full cycle that a point completes after last passing through the reference position. Two periodic motions are said to be in phase when corresponding points of each reach maximum or minimum displacements at the same time. If the crests of two waves pass the same point at the same time, they are in phase for that position. If the crest of one and the trough of the other pass the same point at the same time, the phase angles differ by 180° and the waves are said to be of opposite phase. Phase differences are important in alternating electric current technology (see alternating current).
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In simpler terms, a PLL compares the frequencies of two signals and produces an error signal which is proportional to the difference between the input frequencies. The error signal is used to drive a voltage-controlled oscillator (VCO) which creates an output frequency. The output frequency is fed through a frequency divider back to the input of the system, producing a negative feedback loop. If the output frequency drifts, the error signal will increase, driving the frequency in the opposite direction so as to reduce the error. Thus the output is locked to the frequency at the other input. This input is called the reference and is derived from a crystal oscillator, which is very stable in frequency.
Phase-locked loops are widely used in radio, telecommunications, computers and other electronic applications. They may generate stable frequencies, recover a signal from a noisy communication channel, or distribute clock timing pulses in digital logic designs such as microprocessors. Since a single integrated circuit can provide a complete phase-locked-loop building block, the technique is widely used in modern electronic devices, with output frequencies from a fraction of a cycle per second up to many gigahertz.
In analog television receivers since at least the late 1930s, phase-locked-loop horizontal and vertical sweep circuits are locked to synchronization pulses in the broadcast signal.
When Signetics introduced a line of monolithic integrated circuits that were complete phase-locked loop systems on a chip in 1969, applications for the technique multiplied. A few years later RCA introduced the "CD4046" CMOS Micropower Phase-Locked Loop, which became a popular integrated circuit.
Both analog and digital PLL circuits include three basic elements:
Analog PLLs are generally built of a phase detector, low pass filter and voltage-controlled oscillator (VCO) placed in a negative feedback closed-loop configuration. There may be a frequency divider in the feedback path or in the reference path, or both, in order to make the PLL's output signal frequency an integer multiple of the reference. A non integer multiple of the reference frequency can be created by replacing the simple divide-by-N counter in the feedback path with a programmable pulse swallowing counter. This technique is usually referred to as a fractional-N synthesizer or fractional-N PLL.
The oscillator generates a periodic output signal. Assume that initially the oscillator is at nearly the same frequency as the reference signal. Then, if the phase from the oscillator falls behind that of the reference, the phase detector changes the control voltage of the oscillator, so that it speeds up. Likewise, if the phase creeps ahead of the reference, the phase detector changes the control voltage to slow down the oscillator. A low-pass filter smooths out abrupt changes in the control voltage; it can be demonstrated that some filtering is required for a stable system. Since initially the oscillator may be far from the reference frequency, practical phase detectors may also respond to frequency differences, so as to increase the lock-in range of allowable inputs.
Depending on the application, either the output of the controlled oscillator, or the control signal to the oscillator, provides the useful output of the PLL system.
There are several types of phase detectors in two main categories of analog and digital.
The analog phase detector takes the form of an ideal frequency mixer. This device produces an output that is the product of the two instantaneous input voltages. The multiplication process produces the classical sum and difference frequencies of mixers, but when used as a phase detector, a Low-pass filter is required to attenuate the sum frequency. When the remaining difference frequency is low enough to pass through the filter with sufficient amplitude, it moves the VCO frequency closer to the reference frequency allowing the loop, after a transient period, to acquire lock. This process is called "capture" and the maximum frequency separation (between reference input and VCO) that allows lock is the "capture range". The loop is called "locked" when the VCO is on the same frequency as the reference and differs only in some amount of phase.
When the loop is locked, the sum and difference are still present, but the sum becomes a frequency twice that of the reference. The difference, which appears as the average value of the sum frequency, becomes, after the filter, a DC component proportional to the (cosine of the) phase difference. This then sets the VCO frequency.
The phase difference at the inputs, when in lock, is near 90 degrees for this type; the exact amount being determined by the loop gain. Though an additional integration can be added to bring it to 90, this is rarely required in simple loops.
The phase and amplitude characteristics of the low-pass filter are dominant factors in determining the capture range, lock time and transient performance of the loop.
Two common implementations are the double balanced diode mixer and the four-quadrant multiplier (which is also a double balanced mixer).
The presence of the sum frequency at the mixer output also adds complexity in applications where spectral purity of the VCO signal is important. This causes frequency modulation of the VCO at twice the reference frequency. The resulting unwanted (spurious) sidebands, also called "reference spurs" can dominate the filter requirements and reduce the capture range and lock time well below the requirements. In these applications the more complex digital phase detectors are used which do not have as severe a reference spur component on their output.
A more complex digital PD uses a simple state machine to determine which of the two signals has a zero-crossing earlier or more often. This brings the PLL into lock even when it is off frequency and is known as a Phase Frequency Detector.
A PLL with a bang-bang charge pump phase detector supplies current pulses with fixed total charge, either positive or negative, to the capacitor acting as an integrator. A phase detector for a bang-bang charge pump must always have a dead band where the phases of the reference and feedback clocks are close enough that the detector fires either both or neither of the charge pumps, for no total effect. Bang-bang phase detectors are simple, but are associated with significant minimum peak-to-peak jitter, because once in lock the phase offset drifts inside the two extreme values of the dead band without triggering any corrections.
A proportional phase detector employs a charge pump that supplies charge amounts in proportion to the phase error detected. Some have dead bands and some do not. A dead band is an area where small changes in phase difference produce no correction to the VCO. Specifically, some designs produce both "up" and "down" control pulses even when the phase difference is zero. These pulses are small, nominally the same duration, and cause the charge pump to produce equal-charge positive and negative current pulses when the phase is perfectly matched. If the inputs are slightly mismatched, either the up or down pulse will contain slightly more charge than the other and the PLL will be able to correct the offset. PLLs with this kind of control system don't exhibit a dead band and typically have lower minimum peak-to-peak jitter that is determined by other limiting factors.
These types, having outputs consisting of very narrow pulses at lock, are very useful for applications requiring very low VCO spurious outputs. The narrow pulses contain very little energy and are easy to filter out of the VCO control voltage. This results in low VCO control line ripple and therefore low FM sidebands on the VCO.
It is frequently required to know when the loop is out of lock. The more complex digital phase-frequency detectors usually have an output that allows a reliable indication of an out of lock condition.
A voltage-controlled capacitor is one method of making an LC oscillator vary its frequency in response to a control voltage. Any reverse-biased semiconductor diode displays a measure of voltage-dependent capacitance and can be used to change the frequency of an oscillator by varying a control voltage applied to the diodes. Special-purpose variable capacitance varactor diodes are available with well-characterized wide-ranging values of capacitance. Such devices are very convenient in the manufacture of voltage-controlled oscillators (a voltage-controlled inductor would be in principle as useful, but such devices are unsatisfactory at the frequencies usually desired).
Crystal oscillators are piezoelectric quartz crystals that mechanically vibrate between two slightly different shapes. Crystals have very high Q, and can only be tuned within a very small range of frequencies. Crystal oscillators are typically used as the frequency reference for PLLs, and can be found in nearly every consumer electronic device. Because the crystal is an off-chip component, it adds some cost and complexity to the system design, but the crystal itself is generally quite inexpensive.
For a PLL built into a microprocessor chip, ring oscillators can be used as voltage-controlled oscillators-a free running multivibrator (VCOs). They are built of a ring of active delay stages. Generally the ring has an odd number of inverting stages, so that there is no single stable state for the internal ring voltages. Instead, a single transition propagates endlessly around the ring. The frequency is controlled by varying either the supply voltage or the capacitive loading on each stage. VCOs generally have the lowest Q of the used oscillators, and so suffer more jitter than the other types. The jitter can be made low enough for many applications (such as driving an ASIC), in which case VCOs enjoy the advantages of having no off-chip components (expensive) or on-chip inductors (low yields on generic CMOS processes). These oscillators also have larger tuning ranges than the other kinds, which improves yield and is sometimes a feature of the end product (for instance, the dot clock on a graphics card which drives a wide range of monitors).
Some PLLs also include a divider between the reference clock and the reference input to the phase detector. If this divider divides by , it allows the VCO to multiply the reference frequency by . It might seem simpler to just feed the PLL a lower frequency, but in some cases the reference frequency may be constrained by other issues, and then the reference divider is useful. Frequency multiplication in a sense can also be attained by locking the PLL to the 'N'th harmonic of the signal.
the VCO frequency may be written as a function of the VCO input as
Hence the VCO output takes the form
= A_r cos(omega_f t + varphi(t) )where
The loop filter receives this signal as input and produces an output
When the loop is closed, the output from the loop filter becomes the input to the VCO thus
We can deduce how the PLL reacts to a sinusoidal input signal:
The output of the phase detector then is:
This can be rewritten into sum and difference components using trigonometric identities:
As an approximation to the behaviour of the loop filter we may consider only the difference frequency being passed with no phase change, which enables us to derive a small-signal model of the phase-locked loop. If we can make , then the can be approximated by its argument resulting in: . The phase-locked loop is said to be locked if this is the case.
The loop characteristics can be controlled by inserting different types of loop filters. The simplest filter is a one-pole RC circuit. The loop transfer function in this case is:
The loop response becomes:
This is the form of a classic harmonic oscillator. The denominator can be related to that of a second order system:
For the one-pole RC filter,
The loop natural frequency is a measure of the response time of the loop, and the damping factor is a measure of the overshoot and ringing. Ideally, the natural frequency should be high and the damping factor should be near 0.707 (critical damping). With a single pole filter, it is not possible to control the loop frequency and damping factor independently. For the case of critical damping,
A slightly more effective filter, the lag-lead filter includes one pole and one zero. This can be realized with two resistors and one capacitor. The transfer function for this filter is
This filter has two time constants
Substituting above yields the following natural frequency and damping factor
The loop filter components can be calculated independently for a given natural frequency and damping factor
Typically, the reference clock enters the chip and drives a phase locked loop (PLL), which then drives the system's clock distribution. The clock distribution is usually balanced so that the clock arrives at every endpoint simultaneously. One of those endpoints is the PLL's feedback input. The function of the PLL is to compare the distributed clock to the incoming reference clock, and vary the phase and frequency of its output until the reference and feedback clocks are phase and frequency matched. From a control theory perspective, the PLL is a special case of the Kalman filter.
PLLs are ubiquitous -- they tune clocks in systems several feet across, as well as clocks in small portions of individual chips. Sometimes the reference clock may not actually be a pure clock at all, but rather a data stream with enough transitions that the PLL is able to recover a regular clock from that stream. Sometimes the reference clock is the same frequency as the clock driven through the clock distribution, other times the distributed clock may be some rational multiple of the reference.
Phase noise is another type of jitter observed in PLLs, and is mostly caused by the amplifier elements used in the circuit. Some technologies are known to perform better than others in this regard. The best digital PLLs are constructed with emitter-coupled logic (ECL) elements, at the expense of high power consumption. To keep phase noise low in PLL circuits, it is best to avoid saturating logic families such as transistor-transistor logic (TTL) or CMOS.
Another desirable property of all PLLs is that the phase and frequency of the generated clock be unaffected by rapid changes in the voltages of the power and ground supply lines, as well as the voltage of the substrate on which the PLL circuits are fabricated. This is called supply and substrate noise rejection. The higher the noise rejection, the better.
Frequency Synthesizer manufacturers include Analog Devices, National Semiconductor and Texas Instruments. VCO manufacturers include Sirenza, Z-Communications, Inc. (Z-COMM)
Other applications include: