PA-RISC is nearing the end of its life. HP will support servers running PA-RISC chips until 2013, but will stop selling the latest HP 9000 systems in 2008. Newer Itanium-based machines are supposed to succeed PA-RISC in its market segment.
The early PA-RISC chips were 32-bit designs. They were first used in a new series of HP 3000 machines in the late 1980s — the 930 and 950, commonly known at the time as Spectrum systems, the name given to them in the development labs. These machines ran MPE/iX. The HP 9000 machines were soon upgraded with the PA-RISC processor as well, running the HP-UX version of UNIX.
An interesting aspect of the PA-RISC line is that most of its generations have no Level 2 cache. Instead large Level 1 caches are used, formerly as separate chips connected by a bus, and now integrated on-chip. Only the PA-7100LC and PA-7300LC had L2 caches. Another innovation of the PA-RISC was the addition of vectorized instructions (SIMD) in the form of MAX which were first introduced on the PA-7100LC.
The design was upgraded in 1996 to the PA-RISC 2.0 architecture, which is fully 64-bit. The PA-RISC 2.0 architecture added fused multiply-add instructions, which helps speed up floating-point calculations. The first product of this series was the PA-8000, which featured ten functional units and an aggressive pipelining system. Another change was the splitting of the instruction cache, with separate caches for instructions that take long or short time to complete. The PA-8200 was released in 1997 and was much like the PA-8000 with better branch prediction, lower TLB miss rates, and larger, faster caches.
The PA-8500 design added the cache to the main chip, with 1.5 MB of Level 1 cache. Consequently, it was a great performer for its time. With its introduction the Runway bus was upgraded to a DDR implementation providing ~2 GB/s peak bandwidth to memory. Its branch history table was doubled in size to 2048 entries and its translation lookaside buffer was increased from 120 to 160 entries.
The 8600 is essentially a higher clocked 8500 with a quasi-LRU instruction cache eviction policy. The 8700 is clocked higher than the 8600, to which it is otherwise similar, and has 2.25 MB of L1 cache. It also gained a quasi-LRU data cache eviction policy and data prefetch capability. It is worth noting that the relatively high latencies of the integrated L1, a tradeoff due to its size, may limit performance. However, the size of HP's integrated caches remain impressive for their process sizes.
The PA-8800, codenamed Mako, features 2 independent microprocessors on a single die. Thus each "chip" forms a 2-way SMP set. Each processor on the 8800 has a 1.5 MB L1 cache, but HP is leaving behind its L1-only design custom by including 32 MB of L2 cache using separate chips. The Runway bus has been replaced by the 6.4 GB/s zx1 bus, allowing greater bandwidth and the use of otherwise very similar server designs for both PA-RISC and Itanium.
The PA-8900 is similar to the 8800, but features a faster 64 MB shared L2 and slight core improvements such as better error detection and correction on caches. It is not a die shrink of the 8800, as was earlier rumored. It is the last in the PA-RISC line.
The core design introduced with the PA-8000 has not changed significantly to date; each later generation has concentrated only on increasing clock speed and integrating incremental improvements like larger caches and, finally, 2 cores on one chip.
|Marketing name||Year||Frequency [MHz]||Memory Bus [MB/s]||Process [µm]||Transistors [millions]||Die size [mm²]||Power [W]||Dcache [kB]||Icache [kB]||L2 cache [MB]||ISA|