Manufacturing test, as post-production chip testing is called, comprises a growing fraction of a modern IC device's total cost. Because of this, Design For Test (DFT) has shifted from an afterthought to a distinct design activity of a chip development cycle.
The main purpose of BIST is to reduce the complexity, and thereby decrease the cost and reduce reliance upon external (pattern-programmed) test equipment. BIST reduces cost in two ways: (1) reduces test-cycle duration; and (2) reduces the complexity of the test/probe setup, by reducing the number of I/O signals that must be driven/examined under tester control. Both lead to a reduction in hourly charges for automated test equipment (ATE) service.
Outside of manufacturing test, BIST can be designed to perform field-diagnostics of individual devices or entire systems. For example, at power-up, nearly all modern computer peripherals (printers, monitors, PCs) perform a limited self-diagnostic. Failure of the diagnostic is reported to the user. Sometimes these diagnostics will utilize BIST in the hardware to verify that buses, I/O's and major registers are operating.
The BIST name and concept originated with the idea of including a pseudo-random (PSR) number generator and CRC on the IC. If all the registers that hold state in an IC are on one or more internal scan chains, then the function of the registers and the combinatorial logic between them will generate a unique CRC signature over a large enough sample of random inputs. So all an IC need do is store the expected CRC signature and test for it after a large enough sample set from the PSR. The internal scan chain concept is formalized in the JTAG IEEE 1149.1 standard.
There are several specialized versions of BIST which are differentiated according to what they do or how they are implemented: