Every CPU model has its own machine code, or instruction set. Successor or derivative processor designs may completely include all the instructions of a predecessor and may add additional instructions. Some nearly completely compatible processor designs may have slightly different effects after similar instructions. Occasionally a successor processor design will discontinue or alter the meaning of a predecessor's instruction code, making migration of machine code between the two processors more difficult. Even if the same model of processor is used, two different systems may not run the same example of machine code if they differ in memory arrangement, operating system, or peripheral devices because the machine code has no embedded information about the configuration of the system.
A machine code instruction set may have all instructions of the same length, or may have variable-length instructions. How the patterns are organized depends largely on the specification of the machine code. Common to most is the division of one field (the opcode) which specifies the exact operation (for example "add"). Other fields may give the type of the operands, their location, or their value directly (operands contained in an instruction are called immediate). Some exotic instruction sets do not have an opcode field (such as Transport Triggered Architectures or the Forth virtual machine), only operand(s). Other instruction sets lack any operand fields, such as NOSCs
Program flow may be influenced by special 'jump' instructions that transfer execution to an instruction other than the following one. Conditional jumps are taken (execution continues at another address) or not (execution continues at the next instruction) depending on some condition.
00000101, which causes the CPU to decrement the
Bprocessor register, would be represented in assembly language as
6 5 5 5 5 6 bits
[ op | rs | rt | rd |shamt| funct] R-type
[ op | rs | rt | address/immediate] I-type
[ op | target address ] J-type
rs, rt, and rd indicate register operands; shamt gives a shift amount; and the address or immediate fields contain an operand directly.
For example adding the registers 1 and 2 and placing the result in register 6 is encoded:
[ op | rs | rt | rd |shamt| funct]
0 1 2 6 0 32 decimal
000000 00001 00010 00110 00000 100000 binary
Load a value into register 8, taken from the memory cell 68 cells after the location listed in register 3:
[ op | rs | rt | address/immediate]
35 3 8 68 decimal
100011 00011 01000 00000 00001 000100 binary
Jumping to the address 1024:
[ op | target address ]
2 1024 decimal
000010 00000 00000 00000 00100 000000 binary
Using a microcode layer to implement an emulator enables the computer to present the architecture of an entirely different computer. The System/360 line used this to allow porting programs from earlier IBM machines to the new family of computers, e.g. an IBM 1401/1440/1460 emulator on the IBM S/360 model 40.