Like the IAS machine, JOHNNIAC used 40-bit words, and included 1024 words of Selectron tube main memory, each holding 256 bits of data. Two instructions were stored in every word in 20-bit subwords consisting of an 8-bit instruction and a 12-bit address, the instructions being operated in series with the left subword running first. The initial machine had 83 instructions. A single A register supplied an accumulator, and the machine also featured a Q, for quotient, register as well. There was only one test condition, whether or not the high bit of the A register was set. There were no index registers, and as addresses were stored in the instructions, loops had to be implemented by modifying the instructions as the program ran. Since the machine only had 10 bits of address space, two of the address bits were unused and were sometimes used for data storage by interleaving data through the instructions.
Numerous modifications were made to the system over its lifetime. In March 1955 4096 words of core memory were added to the system, replacing the earlier Selectrons. This required all 12 bits of addressing, and caused programs that stored data in the "spare bits" to fail. Later in 1955 a 12k-word drum memory secondary storage system was added as well. A transistor-based adder replaced the original tube-based one in 1956. Numerous changes were made to the input/output peripherals as well, and in 1964 a real time clock was added to support time sharing.
The Cyclone at Iowa State University was a direct clone of JOHNNIAC, and was instruction compatible with it (the ILLIAC I may have been as well). Cyclone was later updated to include a hardware floating point system.