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AND-OR-Invert (AOI) logic and AOI gates are two-level compound (or complex) logic functions constructed from the combination of one or more AND gates followed by a NOR gate. Construction of AOI cells is particularly efficient using CMOS technology where the total number of transistor gates can be reduced compared to the a same construction using NAND logic or NOR logic. The compliment of AOI Logic is OR-AND-Invert (OAI) logic where the OR gates precede an AND gate.

$F=overline\{(A\; wedge\; B)\; vee\; (C\; wedge\; D)\}$

2-2 AOI | ||||

INPUT A B C D | OUTPUT F | |||

0 | X | X | 0 | 1 |

X | 0 | X | 0 | 1 |

0 | X | 0 | X | 1 |

X | 0 | 0 | X | 1 |

1 | 1 | X | X | 0 |

X | X | 1 | 1 | 0 |

A 2-1 AOI gate can be represented by following the boolean equation and truth table:

$F=overline\{\; A\; vee\; (B\; wedge\; C)\}$

2-1 AOI | |||

INPUT A B C | OUTPUT F | ||

0 | 0 | 0 | 1 |

0 | 0 | 1 | 1 |

0 | 1 | 0 | 1 |

0 | 1 | 1 | 0 |

1 | 0 | 0 | 0 |

1 | 0 | 1 | 0 |

1 | 1 | 0 | 0 |

1 | 1 | 1 | 0 |

Larger AOI gates, such as 4-3 AOI or 3-3-3 AOI can also be used.

AOI gates can be readily implemented in CMOS circuitry. AOI gates are particularly advantaged in that the total number of transistors (or gates) is less than if the AND, NOT, and OR functions were implemented separately. This results in increased speed, reduced power, smaller area, and potentially lower fabrication cost. For example, a 2-1 AOI gate can be constructed with 6 transistors in CMOS compared to 10 transistors using a 2-input NAND gate (4 transistors), an inverter (2 transistors), and a 2-input NOR gate (4 transistors).

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Last updated on Monday September 01, 2008 at 13:31:40 PDT (GMT -0700)

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This article is licensed under the GNU Free Documentation License.

Last updated on Monday September 01, 2008 at 13:31:40 PDT (GMT -0700)

View this article at Wikipedia.org - Edit this article at Wikipedia.org - Donate to the Wikimedia Foundation

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