A complex instruction set computer (CISC, pronounced like "sisk") is a microprocessor instruction set architecture (ISA) in which each instruction can execute several low-level operations, such as a load from memory, an arithmetic operation, and a memory store, all in a single instruction. The term was retroactively coined in contrast to reduced instruction set computer (RISC).
One reason for this was that architects (microcode writers) sometimes "over-designed" assembler language instructions, i.e. including features which were not possible to implement efficiently on the basic hardware available. This could, for instance, be "side effects" (above conventional flags), such as the setting of a register or memory location that were perhaps seldom used; if this were done via ordinary (non duplicated) internal buses (or even the external bus), it would demand extra cycles every time, and thus be quite inefficient.
Even in balanced high performance designs, such (relatively) high level instructions which are typically also highly encoded (for good code density), could be complicated to decode and execute efficiently within a limited transistor budget. These architectures therefore require a great deal of work on the part of the processor designer in cases where a simpler, but (normally) slower, solution based on decode tables and/or microcode sequencing is not appropriate. At the time where transistors were a limited resource, this also left less room on the processor to optimize performance in other ways, which gave room for ideas to return to simpler processor-designs in order to make it more feasible to cope without ROMs (or even PLAs) for sequencing or decoding. This led to the first RISC-labeled processors in the mid-1970s (IBM 801 - IBMs Watson Research Center).
Transistors for logic, PLAs, and microcode are no longer a scarce resource however (only for huge caches, basically), and together with better tools and new technologies, this has led to new implementations of highly encoded and variable length designs without load-store limitations (i.e. non RISC). This governs both re-implementations of older instruction-sets (such as the ubiquitous x86, see below), as well as new designs for microcontrollers for embedded systems, and similar uses.
The terms RISC and CISC have become less meaningful with the continued evolution of both CISC and RISC designs and implementations. The first highly pipelined "CISC" implementations, such as 486s from Intel, AMD, Cyrix, and IBM, certainly supported every instruction that their predecessors did, but achieved high efficiency only on a fairly simple x86 subset (resembling a RISC instruction set, but without the load-store limitations of RISC). Modern x86 processors also decode and split more complex instructions into a series of smaller internal "micro-operations" which can thereby be executed in a pipelined (parallel) fashion, thus achieving high performance on a much larger subset of instructions.