instruction mnemonic


MMIX may also refer to the year 2009, in Roman numerals.

MMIX (pronounced em-mix) is a 64-bit RISC instruction set architecture (ISA) designed by Donald Knuth, with significant contributions by John L. Hennessy (who contributed to the design of the MIPS processor) and Richard L. Sites (who was an architect of the DEC Alpha processor). In Knuth’s own words:

Its purpose for education is quite similar to John L. Hennessy's and David A. Patterson's DLX architecture, from Computer Architecture: A Quantitative Approach.


MMIX is a 64-bit RISC computer, with 256 64-bit general-purpose registers and 32 64-bit special-purpose registers. MMIX is a big-endian machine with 32-bit instructions and a 64-bit virtual address space. The MMIX instruction set comprises 256 opcodes, one of which is reserved for future expansion.


All instructions have an associated mnemonic. For example instruction 32 is associated to ADD. Most instructions have the symbolic form "OP X,Y,Z", where OP specifies the sort of instruction, X specifies the register used to store the result of the instruction and the rest specify the operands of the instruction. Each of these fields is eight bits wide. For example, the instruction "ADD $0,$1,3", will add the contents of register 1 and the immediate value 3 and store the result in register 0.

Most instructions can take either immediate values or register contents; thus a single instruction mnemonic may correspond to one of two opcodes.

MMIX programs are typically constructed using the MMIXAL assembly language. For an example see Transwiki:List of hello world programs#General-purpose fictional computer: MMIX, MMIXAL.


There are 256 general purpose architectural registers in an MMIX chip, designated by $0 through $255 and 32 special physical architectural registers. They are implemented by 256-32=224 global physical registers and 512 local physical registers. If X is a number from 0 to 255 inclusive, then special registers rL and rG determine whether register $X refers to a local or a global physical register.

Local register stack

The local register stack provides each subroutine with its own rL local registers, designated by $0 through $(rL−1). Whenever a subroutine is called, a number of local registers is pushed down the stack. The arguments of the called subroutine are left in the remaining local registers. When a subroutine finishes it pops the previously pushed registers. Because there are only 512 local physical registers, it may be necessary to store a part of the stack in memory. This is implemented with the special registers rO and rS which record which part of the local register stack is in memory and which part is still in local physical registers. The register stack provides for fast subroutine linkage.

Special registers

The 32 special physical architectural registers are as follows:

  1. ;rB, the bootstrap register (trip)
  2. : When tripping, rB <- $255 and $255 <- rJ. Thus saving rJ in a general register.
  3. rD, the dividend register
  4. : Unsigned integer divide uses this as the left half of the 128-bit input that is to be divided by the other operand.
  5. rE, the epsilon register
  6. : Used for floating comparisons with respect to epsilon.
  7. rH, the himult register
  8. : Used to store the left half of the 128-bit result of unsigned integer multiplication.
  9. rJ, the return-jump register
  10. : Used to save the address of the next instruction by PUSHes and by POP to return from a PUSH.
  11. rM, the multiplex mask register
  12. : Used by the multiplex instruction.
  13. rR, the remainder register
  14. :Is set to the remainder of integer division.
  15. rBB, the bootstrap register (trap)
  16. : When trapping, rBB <- $255 and $255 <- rJ. Thus saving rJ in a general register
  17. rC, the cycle counter
  18. : Incremented every cycle.
  19. rN, the serial number
  20. : A constant identifying this particular MMIX processor.
  21. rO, the register stack offset
  22. : Used to implement the register stack.
  23. rS, the register stack pointer
  24. : Used to implement the register stack.
  25. rI, the interval counter
  26. : Decremented every cycle. Causes an interrupt when zero.
  27. rT, the trap address register
  28. : Used to store the address of the trip vector.
  29. rTT, the dynamic trap address register
  30. : Used to store the address of the trap vector.
  31. rK, the interrupt mask register
  32. : Used to enable and disable specific interrupts.
  33. rQ, the interrupt request register
  34. : Used to record interrupts as they occur.
  35. rU, the usage counter
  36. : Used to keep a count of executed instructions.
  37. rV, the virtual translation register
  38. : Used to translate virtual addresses to physical addresses. Contains the size and number of segments, the root location of the page table and the address space number.
  39. rG, the global threshold register
  40. : All general registers references with a number greater or equal to rG refer to global registers.
  41. rL, the local threshold register
  42. : All general registers references with a number smaller than rL refer to local registers.
  43. rA, the arithmetic status register
  44. : Used to record, enable and disable arithmetic exception like overflow and divide by zero.
  45. rF, the failure location register
  46. : Used to store the address of the instruction that caused a failure.
  47. rP, the prediction register
  48. : Used by conditional swap (CSWAP).
  49. rW, the where-interrupted register (trip)
  50. : Used, when tripping, to store the address of the instruction after the one that was interrupted.
  51. rX, the execution register (trip)
  52. : Used, when tripping, to store the instruction that was interrupted.
  53. rY, the Y operand (trip)
  54. : Used, when tripping, to store the Y operand of the interrupted instruction.
  55. rZ, the Z operand (trip)
  56. : Used, when tripping, to store the Z operand of the interrupted instruction.
  57. rWW, the where-interrupted register (trap)
  58. : Used, when trapping, to store the address of the instruction after the one that was interrupted.
  59. rXX, the execution register (trap)
  60. : Used, when trapping, to store the instruction that was interrupted.
  61. rYY, the Y operand (trap)
  62. : Used, when trapping, to store the Y operand of the interrupted instruction.
  63. rZZ, the Z operand (trap)
  64. : Used, when trapping, to store the Z operand of the interrupted instruction.

Hardware implementations

As of 2008, the MMIX instruction set architecture has not yet been implemented in hardware.

Software tools

The MMIX instruction set architecture is supported by a number of software tools for computer architecture research and software development.

Simulators and assembler

  • MMIXware (version 20060918) – Donald Knuth’s MMIX-SIM simple (behavioral) simulator, MMIXAL assembler, test suite, sample programs, full documentation, and MMMIX architectural (pipeline) simulator. (gzipped tar file.)
  • MMIXX – An X11-based graphics package contributed by Andrew Pochinsky of MIT’s Center for Theoretical Physics which, when combined with the MMIXware sources above, augments the MMIX virtual machine with a VGA-resolution, true-color ‘virtual display.’ (For UNIX/Linux.)


The GNU Compiler Collection includes an MMIX back-end for its C/C++ compilers, contributed by Hans-Peter Nilsson and part of the main GCC distribution since late 2001.


  • Errata to above book.
  • Donald E. Knuth (2005). The Art of Computer Programming Volume 1 Fascicle 1: MMIX A RISC Computer for the New Millennium. Addison-Wesley. ISBN 0-201-85392-2 (errata)

External links

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