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graphic workstation

PDP-11

The PDP-11 was a series of 16-bit minicomputers sold by Digital Equipment Corp. from 1970 into the 1990s. The PDP-11 was a successor to DEC's PDP-8 computer in the PDP series of computers. It had several uniquely innovative features, and was easier to program than its predecessors. It was well-liked by programmers, and it was replaced in the mid-range minicomputer niche by the VAX-11 32-bit extension of the PDP-11. Much of the market for both machines would be taken by personal computers, including the IBM PC and Apple II, and workstations, such as those from Sun Microsystems.

Unique features of the PDP-11 Series

Instruction set

Programmers liked the PDP-11 design because it had a highly-orthogonal instruction set which allowed them to separately memorize all of the operations and the methods of accessing operands. They could then predict that any access method (or "addressing mode") would work with any operation; they did not have to learn a list of exceptions or special cases in which an operation had a special or restricted set of addressing modes.

A (false) folk myth is that the instruction set architecture of the PDP-11 influenced the idiomatic use of the C programming language. The PDP-11's increment and decrement addressing modes correspond to the −−i and i++ constructs in C. If i and j were both register variables, an expression such as *(−−i) = *(j++) could be compiled to a single machine instruction. A further claim is that the lack of different opcodes for single and double floating point operations resulted in the mapping of single precision operations to double precision in the language. Dennis Ritchie unambiguously contradicts this folk myth.

In some logical sense, the set of addressing modes provided one "basis", and the set of operations provided another. Each two-operand instruction was separated into two six-bit operand identifiers (each consisting of a three-bit register number, and a three-bit addressing mode) and a four-bit op-code; single-operand instructions had one six-bit operand identifier, and a ten-bit op-code. All op-codes operated with any operand identifier address mode (or combination of them, for the two-operand instructions). Of the 8 registers (numbered 0 through 7), 7 were general-purpose and could be used for most purposes, although register 6 was specially recognized by the hardware as the stack pointer for some instructions; register 7 was the program counter. This latter innovation, together with some of the addressing modes, provided constants, absolute addresses, and relative (position independent) addressing.

16-bit words were stored little-endian with least significant bytes first. Due to the popularity of the PDP-11, this format is still sometimes referred to as pdp-endian. 32-bit data (supported as extensions to the basic architecture, e.g., floating point in the FPU Instruction Set, double-words in the Extended Instruction Set or long data in the Commercial Instruction Set) were stored in more than one format, including an unusual middle-endian format.

No dedicated I/O bus

In the most radical departure from other, earlier computers, the initial models of the PDP-11 had no dedicated bus for input/output; it had only a memory bus called the Unibus. All input and output devices were mapped to memory addresses, so no special I/O instructions were needed.

Higher performance members of the PDP-11 family, starting with the PDP-11/45, departed from the single bus approach. Instead, memory was interfaced by dedicated circuitry and space in the CPU cabinet, while the Unibus continued to be used for I/O only. In the PDP-11/70 this was taken a step further, with the addition of a dedicated interface from disks and tapes, via the Massbus to memory. Nevertheless I/O device address space and memory address space remained congruent: the control, status, and data registers of I/O device controllers were addressed by referencing particular memory addresses, with no special I/O instructions.

Interrupts

The interrupt system was intentionally designed to be as simple as possible, while ensuring that no event in an interrupt sequence could be missed. A device would request an interrupt by asserting a common input into one of four priority lines; the processor would respond over an interrupt daisy chain grant line, one for each priority level. (A daisy chain is a sequence of logic gates arranged in series to order events. Generally the first logic gate has first access to the grant. The daisy chain order established the order of the devices at that priority level.)

In the case of the PDP-11 design, this meant that the interrupt grant order was determined by how close the physical hardware was to the CPU on the bus. When the CPU responded, the device would place its vector address on the bus; this was the address of a 4-byte block of memory. The CPU would then load the status register and program counter from the vector table; the new contents of the status register would generally temporarily disable interrupts. The address in the program counter would be the starting address of the code to run for the interrupt. The interrupt code would then service the device, and in the process, write to the interrupting device to re-enable the interrupt signal. Finally, a special RTI (return from interrupt) instruction would return the CPU to where it was before the interrupt (which might have been in a lower-priority interrupt). Note that this process prevents loss of interrupts; at every stage, if the interrupt is not serviced, it remains in place, to be sensed on the next cycle. If a sequence were erroneously started (as from a defective device controller), the CPU would time out, generating a special spurious interrupt; the spurious interrupt would warn users of bad hardware.

Designed for mass production

Finally, the PDP-11 was designed to be produced in a factory by semiskilled labor. All of the dimensions of its pieces were relatively non-critical. It used a wire-wrapped backplane. That is, the printed circuit boards plugged into a backplane connector. The backplane connectors had square pins that could be connected to by wrapping wires around them. The corners of the pins would bite into the wire to form a gas-tight (i.e. corrosion-proof, therefore reliable) connection.

The LSI-11

The LSI-11 (PDP-11/03) was the first PDP-11 model produced using large-scale integration; the entire CPU was contained on 4 LSI chips made by Western Digital (the MCP-1600 chip set). It used a bus which was a close variant of the Unibus called the Q-Bus; it differed from the Unibus primarily in that addresses and data were multiplexed onto a shared set of wires, as opposed to having separate sets of wires, as in the Unibus. It also differed slightly in how it addressed I/O devices and it eventually allowed a 22-bit physical address (whereas the Unibus only allowed an 18-bit physical address) and block-mode operations for significantly improved bandwidth (which the Unibus did not support).

The CPU's microcode includes a debugger that directly communicated to a standard serial RS-232 or current loop terminal. This was useful because the microcode is the part of the irreducible guts of the computer, a critical part of the control unit. If it doesn't work, there is no computer. The debugger provided a way to examine the computer's registers, memory and input and output devices. Thus, if the CPU worked at all, it was possible to examine and correct the computer's internal state. The built-in debugger avoided the expense and inconvenience of a front panel with an array of switches and lights, which was then the typical way to enter digital data into a near-dead computer.

These two innovations meant that most of the time, the computer just worked. If it did not boot from its big disk, it would boot from its floppy. If the hardware worked at all, it talked to you through a terminal in a familiar way.

Later Q-Bus based systems such as the LSI-11/23, /73, and /83 were based upon chip sets designed in house by Digital Equipment Corporation. Later PDP-11 Unibus systems were designed to use similar Q-Bus processor cards, sometimes with a special memory bus for improved speed, using a Unibus adapter to support existing Unibus peripherals.

There were significant other innovations in the Q-Bus lineup. A system variant of the PDP-11/03 introduced full system Power-On Self-Test (POST) and the 11/83 introduced a primitive (by today's standards) anticipatory CPU cache pre-load as well as a high-speed private memory interconnect (bus).

An early publication of Rodnay Zaks from Sybex was A microprogrammed APL implementation ISBN: 0895880059 which is the complete, total source listing for the microcode for a PDP / LSI-11 processor implementing the APL programming language.

The decline of the PDP-11

The basic design was extremely sound, and was continually updated to use newer technologies. Ultimately, however, the 16-bit architecture proved to be a limitation which could not be overcome by tweaks and add-ons. While many models supported larger physical address spaces using memory mapping hardware, at any given moment a program could access only a 16-bit virtual address space: only 64 kilobytes (KB) of memory (with separate address spaces for instructions and for data on some models). Even though inexpensive VLSI memory chips made large amounts of memory readily affordable in the 1980s, PDP-11 software was not capable of effectively using large amounts of memory.

(Actually, through linker/loader(/symbolic debugger) synergy, the 64 KB size limitation for instruction space could be overcome almost without loss of execution efficiency under RT-11SJ, TSXplus, and SHAREplus operating systems by employing a technique which uses dynamical switching of page address register 6 [PAR6] via run-time-system stubs for each procedure outside the currently active 8 KB code page, leaving full 48 KB of the low 16 bit memory capacity for program data, stack, and heap. This method was successfully implemented and used in Modula-2 to write really big programs without the need of overlays. Interestingly, the compiler didn't need any change, except that the compiler, itself written in Modula-2, took advantage of the bigger stack and heap; for more details see external reference below.)

DEC's own successor to the PDP-11, the VAX-11 (for "Virtual Address Extension (to the PDP-11)") addressed all of these issues, but was initially a "super-minicomputer" aimed at the high-end time sharing market. The early VAXes provided a PDP-11 compatibility mode, so that much existing PDP-11 software could be immediately used without significant reprogramming.

As engineers migrated to architectures that supported a larger address space, 32-bit computing began to be supported on microprocessor chips such as the Motorola 68000 and Intel 80386 processors and their successors; eventually the economics of large-scale production of those chips eliminated any cost advantage for the 16-bit PDP-11. A line of personal computers based on the PDP-11, the DEC Professional series, failed commercially, along with other non-PDP-11 PC offerings from DEC.

DEC discontinued PDP-11 production in 1997, and sold the PDP-11 design and system software rights to Mentec, Inc., an Irish producer of LSI-11 based boards for Q-Bus and ISA architecture personal computers. For several years, Mentec produced new PDP-11 processors.

By the late 1990s, not only DEC but most of the New England computer industry which had been built around minicomputers similar to the PDP-11 collapsed in the face of microcomputer-based workstations and servers.

Architectural details

The following information is found in DEC's PDP-11 Processor Handbook (see Gordon Bell's 1969 edition).

General register addressing modes

(R is a general register, 0 to 7; (R) is the contents of that register.)
0. Register - the value is to or from a register: OPR R ; R contains operand
1. Register deferred - register is used as a memory address to read or write: OPR (R) ; R contains address
2. Autoincrement: OPR (R)+ ; R contains address, then increment (R)
3. Autoincrement deferred: OPR @(R)+ ; R contains address of address, then increment (R) by 2
4. Autodecrement: OPR -(R) ; Decrement (R), R contains address
5. Autodecrement deferred: OPR @-(R) ; Decrement (R) by 2, then R contains address of address
6. Index: OPR X(R) ; (R)+X is address, second word of instruction
7. Index deferred: OPR @X(R) ; (R)+X is address (second word) of address

Program counter addressing modes

The program counter (PC) can also be used as a general purpose register, providing the following effectively additional addressing modes, using the mechanisms of the addressing modes above:
2. Immediate: OPR #N ; Operand is contained in the instruction
3. Absolute: OPR @#A ; Absolute address is contained in the instruction
6. Relative: OPR A ; PC+2+X is address. PC+2 is updated PC
7. Relative deferred: OPR @A ; PC+2+X is address of address. PC+2 is updated PC

Memory management

Some PDP-11 processors included memory management to support virtual addressing. The physical address space was extended to 18 or 22 bits, though the logical address space remained limited to 16 bits. Additionally, in some models, beginning with 11/45, the usable address space was doubled by instruction/data space separation. Some operating systems, notably Unix since edition V7, and RSX11-M+, relied on this feature.

PDP-11 instruction repertoire

The PDP-11 possesses a powerful instruction repertoire.

Single Operand instructions

One part of the word specifies the operation, referred to as "opcode" (short for "operation code", the second part provides information for locating the operand.

15 6 5 3 2 0
OP-Code Mode Register

  • CLR (clear)
  • COM (ones complement)
  • INC (increment)
  • DEC (decrement)
  • NEG (twos complement negate)
  • TST (test)
  • ASR (arithmetic shift right)
  • ASL (arithmetic shift left)
  • ROR (rotate right)
  • ROL (rotate left)
  • SWAB (swap bytes)
  • ADC (add carry)
  • SBC (subtract carry)
  • SXT (sign extend)

Double Operand instructions

the first part of the word specifies the operation to be performed, the remaining two parts provide information for locating the operands.

15 12 11 9 8 6 5 3 2 0
OP-Code Mode Register Mode Register

  • MOV (move)
  • ADD
  • SUB (subtract)
  • BIT (bit test)
  • BIC (bit clear)
  • BIS (bit set)
  • XOR (exclusive OR)

Program Control instructions

The first part of the word specifies the operation to be performed, the second part indicates where the action is to take place in the program.

15 8 7 0
OP-Code Offset

  • BR (branch unconditionally)
  • BNE (branch if not zero)
  • BEQ (branch if zero)
  • BPL (branch if plus)
  • BMI (branch if minus)
  • BVC (branch if overflow clear)
  • BVS (branch if overflow set)
  • BCC (branch if carry clear)
  • BCS (branch if carry set)
  • BLE (branch if <= 0)
  • BGE (branch if >= 0)
  • BLT (branch if < 0)
  • BGT (branch if > 0) (signed compares)
  • BLO (branch if lower)
  • BHI (branch if higher)
  • BLOS (branch if lower or same)
  • BHIS (branch if higher or same) (unsigned compares).
  • SOB (subtract one from register and branch if not = 0).

Jump & Subroutine instructions

  • JMP (jump)
  • JSR (jump to subroutine)
  • RTS (return from subroutine)
  • MARK (support of stack clean-up at return)
  • EMT (emulator trap)
  • TRAP, BPT (breakpoint trap)
  • IOT (input/output trap)
  • RTI & RTT (return from interrupt).

Miscellaneous instructions

  • HALT, WAIT (wait for interrupt)
  • RESET (reset UNIBUS)
  • MTPD (move to previous data space)
  • MTPI (move to previous instruction space)
  • MFPD (move from previous data space)
  • MFPI (move from previous instruction space)
  • MTPS (move to processor status word)
  • MFPS (move byte from processor status word).

Condition Code operations

  • CLC, CLV, CLZ, CLN, CCC (clear relevant condition code)
  • SEC, SEV, SEZ, SEN, SCC (set relevant condition code).

The four condition codes in the processor status word (PSW) are

  • N indicating a negative value
  • Z indicating a zero (equal) condition
  • V indicating an overflow condition, and
  • C indicating a carry condition.

SCC and CCC respectively set and clear all four condition codes.

"Extended Instruction Set" (EIS)

The EIS was an option for 11/35/40 and 11/03, and was standard on newer processors.

  • MUL, DIV multiply and divide integer operand to register pair
  • ASH, ASHC arithmetic - shift a register or a register pair. For a positive number it will shift left, and right for a negative one.

"Floating Instruction Set" (FIS)

The FIS instruction set was an option for the PDP-11/35/40 and 11/03

  • FADD, FSUB, FMUL, FDIV only for single-precision operating on stack addressed by register operand

"Floating Point Processor" (FPP)

This was the optional floating point processor option for 11/45 and most subsequent models.

  • full floating point operations on single- or double-precision operands, selected by single/double bit in Floating Point Status Register
  • single-precision floating point data format predecessor of IEEE 754 format: sign bit, 8-bit exponent, 23-bit mantissa with hidden bit 24

"Commercial Instruction Set" (CIS)

The CIS microcode option for 11/23/24, add-in modules for the 11/44, and one version of the 11/74.

  • Various string and decimal instructions used to support COBOL and Dibol.

MACRO-11 assembly language

MACRO-11 is the assembly language for the PDP-11. It is the successor to PAL-11 (Program Assembler Loader), an earlier version of the PDP-11 assembly language without macro facilities. MACRO-11 was supported on all DEC PDP-11 operating systems. PDP-11 Unix systems also include an assembler (called "as"), structurally similar to MACRO-11 but with different syntax and fewer features.

PDP-11 models

The PDP-11 processors tended to fall into several natural groups depending on the original design upon which they are based and which I/O bus they used. Within each group, most models were offered in two versions, one intended for OEMs and one intended for end-users.

Unibus models

The following models used the Unibus as their principal bus:

  • PDP-11 (later renamed the PDP-11/20) and PDP-11/15 — The original, non-microprogrammed processor; designed by Jim O'Loughlin.
  • PDP-11/35 and 11/40 — A microprogrammed successor to the /20; the design team was led by Jim O'Loughlin.
  • PDP-11/45, 11/50, and 11/55 — A much faster microprogrammed processor that could use semiconductor memory instead of or in addition to core memory.
  • PDP-11/70 — The 11/45 architecture expanded to allow 4 MB of physical memory segregated onto a private memory bus, 2 KB of cache memory, and much faster I/O devices connected via the Massbus.
  • PDP-11/05 and 11/10 — A cost-reduced successor to the 11/20.
  • PDP-11/34 and 11/04 — Cost-reduced follow-on products to the 11/35 and 11/05. The PDP-11/09 and 11/39 model names were documented internally to DEC but never produced for sale. The PDP-11/34 concept was created by Bob Armstrong.
  • PDP-11/44 — An extension of the 11/34 that included the cache memory and floating point units as a standard feature. This machine also included a sophisticated serial console and support for 4 MB of physical memory. The design team was managed by John Sofio. NOTE: DEC documentation (PDP-11/44 System User's Guide, EK-11044-UG-003) shows the floating point unit as an option (FPP-11F). Moreover, others have documented the 11/44 as a descendent of the 11/45 and 11/70; the 11/34 was of a different 'lineage', following the 11/05.
  • PDP-11/60 — A PDP-11 with user-writable microcontrol store; this was designed by another team led by Jim O'Loughlin.
  • PDP-11/24 — First VLSI PDP-11 for Unibus, using the "Fonz-11" (F11) chip set
  • PDP-11/84 — Using the VLSI "Jaws-11" (J11) chip set
  • PDP-11/94 — J11-based, faster than 11/84

Q-bus models

The following models used the Q-Bus as their principal bus:

  • PDP-11/03 (also known as the LSI-11/03) — The first LSI PDP-11, this system used a chipset from Western Digital.
  • PDP-11/23 — 2nd generation of LSI (F-11), early units only supported 248 KB memory, but could be modified for 4 MB support
  • PDP-11/23+/MicroPDP-11/23 — Improved 11/23 with more functions on processor card (physically a quad-size card rather than dual)
  • MicroPDP-11/73 — The third generation LSI PDP, this system used the "Jaws-11" (J-11) chip set.
  • MicroPDP-11/53 — slower 11/73 with on-board memory
  • MicroPDP-11/83 — faster 11/73 with PMI (private memory interconnect)
  • MicroPDP-11/93 — faster 11/83; final DEC Q-Bus PDP-11 model.
  • Mentec M100 — Mentec redesign of the 11/93, with J-11 chipset at 19.66 MHz, 4 onboard serial ports, 1-4 MB on-board memory, and optional FPU.
  • Mentec M11 — processor upgrade board; last microcode implementation of PDP-11 instruction set by Mentec, using the TI 8832 ALU and TI 8818 microsequencer from Texas Instruments
  • Quickware QED-993 — high performance PDP-11/93 processor upgrade board

Models without standard bus

  • PDT-11/110
  • PDT-11/130
  • PDT-11/150

The PDT series were desktop systems marketed as "smart terminals". The /110 and /130 were housed in a VT100 terminal enclosure. The /150 was housed in a table-top unit which included two 8" floppy drives, 3 asynchronous serial ports, 1 printer port, 1 modem port and 1 synchronous serial port and required an external terminal. All three employed the same chipset as used on the LSI-11/03 and LSI-11/2 in four "microm"s. There was an option which combined two of the microms into one dual carrier, freeing one socket for an EIS/FIS chip.

  • PRO-325
  • PRO-350
  • PRO-380

The DEC Professional series were desktop PCs intended to compete with IBM's earlier 8088 and 80286 based personal computers. The models were equipped with 5 1/4" floppy disk drives and hard disks, except the 325 which had no hard disk. The original operating system was P/OS, which was essentially RSX-11M+ with a menu system on top. As the design was intended to avoid software exchange with existing PDP-11 models, their ill fate in the market was no surprise for anyone except DEC. RT-11 was eventually ported to the PRO series. A port to the PRO for RSTS/E was also done internal to DEC, but was not released. The PRO-325 and -350 units were based on the DCF-11 ("Fonz") chipset, the same as found in the 11/23, 11/23+ and 11/24. The PRO-380 was based on the DCJ-11 ("Jaws") chipset, the same as found in the 11/53,73,83 and others, though running only at 10 MHz because of limitations in the support chipset.

Models that were planned but never introduced

  • PDP-11/27 — A Jaws-11 implementation that would have used the VAXBI Bus as its principal I/O bus.
  • PDP-11/68 — A follow-on to the PDP-11/60 that would have supported 4 MB of physical memory.
  • PDP-11/74 — A PDP-11/70 that was extended to contain multiprocessing features. Up to four processors could be interconnected, although the physical cable management became unwieldy. Another variation on the 11/74 contained both the multiprocessing features and the Commercial Instruction Set. A substantial number of prototype 11/74's (of various types) were built and at least two multiprocessor systems were sent to customers for beta testing, but no systems were ever officially sold. A four processor system was maintained by the RSX-11 operating system development team for testing and a uniprocessor system served PDP-11 engineering for general purpose timesharing. The 11/74 was due to be introduced around the same time as the announcement of the new 32 bit product line and the first model - the VAX 11/780. Rumour/Legend or conspiracy theory held that the reason the 11/74 was cancelled was due to its higher performance compared to the 11/780 (see, for example ). Marketing was therefore concerned that the availability of a higher performing PDP-11 would slow migration to the new VAX. This was not the case. Rather, the ability to maintain the product in the field was the issue. However conspiracy or not, DEC was never able to successfully migrate its entire PDP-11 customer base to the VAX. The primary reason was not performance, but the PDP-11's superior real-time responsiveness.

Special purpose versions

  • GT40 — VT11 vector graphic terminal using a PDP-11/05
  • GT42 — VT11 vector graphic terminal using a PDP-11/10
  • GT44 — VT11 vector graphic terminal using a PDP-11/40
  • GT62 — VS60 vector graphic workstation using a PDP-11/34a
  • H-11Heathkit OEM version of the LSI-11/03
  • VT20 — Terminal with PDP-11/05 with direct mapped character display for text editing and typesetting (predecessor of the VT71)
  • VT71 — Terminal with LSI-11/03 and QBUS backplane with direct mapped character display for text editing and typesetting
  • VT103 — VT100 with backplane to host an LSI-11
  • VT173 — A high-end typseset terminal containing an 11/03
  • MINC-11 — Laboratory system based on 11/03 or 11/23; when based on the 11/23, it was sold as a 'MINC-23', but many MINC-11 machines were field-upgraded with the 11/23 processor. Early versions of the MINC-specific software package would not run on the 11/23 processor because of subtle changes in the instruction set; MINC 1.2 is documented as compatible with the later processor.
  • C.mmp — Multiprocessor system from Carnegie Mellon University
  • SBC 11/21 (boardname KXT11) Falcon and Falcon Plus — single board computer on a Qbus card implementing the basic PDP11 instruction set, based on T11 chipset containing 32KB static RAM, 2 ROM sockets, 3 serial lines, 20 bits parallel I/O, 3 interval timers and a 2-channel DMA controller. Up to 14 Falcons could be placed into one Qbus system.

Unauthorized clones

The PDP-11 was sufficiently popular that many unauthorized PDP-11-compatible minicomputers and microcomputers were produced in Eastern Bloc countries. At least some of these were pin-compatible with DEC's PDP-11s and could share peripherals and system software. These include:

Operating systems

Several operating systems were available for the PDP-11

From Digital:

From third parties:

See also

  • SIMH (A multiple minicomputer architecture emulator written in portable C.)

Notes

References

Further reading

*

  • Michael Singer, PDP-11. Assembler Language Programming and Machine Organization, John Wiley & Sons, NY: 1980.

External links

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