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# Fan-out

Fan-out is a measure of the ability of a logic gate output, implemented electronically, to drive a number of inputs of other logic gates of the same type. In most designs, logic gates are connected together to form more complex circuits, and it is common for one logic gate output to be connected to several logic gate inputs. The technology used to implement logic gates usually allows gate inputs to be wired directly together with no additional interfacing circuitry required.

A perfect logic gate would have infinite input impedance and zero output impedance, allowing a gate output to drive any number of gate inputs. However, since real-world fabrication technologies exhibit less than perfect characteristics, a limit will be reached where a gate output cannot drive any more current into subsequent gate inputs - attempting to do so causes the voltage to fall below the level defined for the logic level on that wire, causing errors.

The fan-out is simply the number of inputs that can be connected to an output before the current required by the inputs exceeds the current that can be delivered by the output while still maintaining correct logic levels. The current figures may be different for the logic zero and logic one states and in that case we must take the pair that give the lower fan-out. This can be expressed mathematically as

$text\left\{DC Fan-out\right\} = operatorname\left\{min\right\}left \left(leftlfloorfrac\left\{I_\left\{text\left\{out high\right\}\right\}\right\}\left\{I_\left\{text\left\{in high\right\}\right\}\right\}rightrfloor ,leftlfloorfrac\left\{I_\left\{text\left\{out low\right\}\right\}\right\}\left\{I_\left\{text\left\{in low\right\}\right\}\right\}rightrfloor right \right)$
($lfloor;rfloor$ is the floor function).

Going on these figures alone TTL logic gates are limited to perhaps 2 to 10, depending on the type of gate, while CMOS gates have DC fan-outs that are generally far higher than is likely to occur in practical circuits (e.g. using NXP Semiconductor specifications for their HEF4000 series CMOS chips at 25 °C and 15 V gives a fan-out of 34 thousand).

However inputs of real gates have capacitance as well as resistance to the power supply rails. This capacitance will slow the output transition of the previous gate and hence increase its propagation delay. As a result, rather than a fixed fan-out the designer is faced with a trade off between fan-out and propagation delay (which affects the maximum speed of the overall system). This effect is less marked for TTL systems, which is one reason why they maintained a speed advantage over CMOS for many years.

Dynamic or AC fan-out, not DC fan-out, is therefore the primary limiting factor due to the speed limitation. For example, suppose a microcontroller has 3 devices on its address and data lines, and the microcontroller can drive 35 pF of bus capacitance at its maximum clock speed. If each device has 8 pF of input capacitance, then only 11 pF of trace capacitance is allowable. (Routing traces on printed circuit boards usually have 1-2 pF per inch so the traces can be 5.5 inches long max.) If this trace length condition can't be met, then the microcontroller must be run at a slower bus speed for reliable operation. Or a buffer chip with higher current drive must be added- higher current drive increases speed since I= C*dV/dt.

Unfortunately, due to the higher speeds of modern devices, IBIS simulation may be required for exact determination of the dynamic fan-out since dynamic fan-out is not clearly defined in most datasheets. (See the external link for more information.)