In the context of logic design, the term dynamic logic is more commonly and preferably referred to as clocked logic, as it makes clear the distinction between this type of design and static logic, as will be explained in the next section. Unfortunately, the term dynamic logic is also used in the context of artificial intelligence to describe something entirely different. These two uses of the term are unrelated.
To additionally confuse the matter, clocked logic is sometimes used as a synonym for sequential logic; this usage is nonstandard and should be avoided.
In this article, dynamic logic is used.
The largest difference between static and dynamic logic is that in dynamic logic, a clock signal is used to evaluate combinational logic. However, to truly comprehend the importance of this distinction, the reader will need some background on static logic.
In most types of logic design, termed static logic, there is at all times some mechanism to drive the output either high or low. In many of the popular logic styles, such as TTL and traditional CMOS, this principle can be rephrased as a statement that there is always a low-impedance path between the output and either the supply voltage or the ground. As a sidenote, there is of course an exception in this definition in the case of high impedance outputs, such as a tri-state buffer; however, even in these cases, the circuit is intended to be used within a larger system where some mechanism will drive the output, and they do not qualify as distinct from static logic.
In contrast, in dynamic logic, there is not always a mechanism driving the output high or low. In the most common version of this concept, the output is driven high or low during distinct parts of the clock cycle.
As an example, consider first the static logic implementation of a NAND gate (here in CMOS):
This circuit implements the logic function
Consider now a dynamic logic implementation:
The dynamic logic circuit requires two phases. The first phase, when Clock is low, is called the setup phase or the precharge phase and the second phase, when Clock is high, is called the evaluation phase. In the setup phase, the output is driven high unconditionally (no matter the values of the inputs A and B). The capacitor, which represents the load capacitance of this gate, becomes charged. Because the transistor at the bottom is turned off, it is impossible for the output to be driven low during this phase.
During the evaluation phase, Clock is high. If A and B are also high, the output will be pulled low. Otherwise, the output stays high (due to the load capacitance).
Dynamic logic has a few potential problems that static logic does not. For example, if the clock speed is too slow, the output will decay too quickly to be of use.
A popular implementation is domino logic.
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