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In integrated circuit design,
dynamic logic (or sometimes clocked logic) is a design methodology logic family in digital logic that was popular in the 1970s and has seen a recent resurgence in the design of high speed digital electronics, particularly computer CPUs. Dynamic logic is distinguished from so-called static logic in that it uses a clock signal in its implementation of combinational logic circuits, that is, logic circuits in which the output is a function of only the current input. The usual use of a clock signal is to synchronize transitions in sequential logic circuits, and for most implementations of combinational logic, a clock signal is not even needed. To those unfamiliar with the challenges of digital logic design, then, it must seem a disadvantage that clocked logic relies so heavily on a clock signal. As will be shown in this article, however, there are certain circumstances in which dynamic logic has a clear advantage.
## Terminology

## Static versus dynamic logic

## Advantages

Dynamic logic (properly designed) is over twice as fast as normal logic. It uses only fast N transistors, and is amenable to transistor sizing optimizations. Static logic is slower because it has twice the loading, higher thresholds, and actually uses slow P transistors to compute things. Dynamic logic may be harder to work with, but if you need the speed, there is no other choice. Anything you buy that runs over 2 GHz in 2007 uses dynamic logic. Another advantage is low power. A dynamic logic circuit running at 1/2 voltage will consume 1/4 the power of normal logic. Also each rail can convey an arbitrary number of bits, and there are no power-wasting glitches. Also power-saving clock gating and asynchronous techniques are much more natural in dynamic logic.
## Dynamic logic example

## External links

In the context of logic design, the term dynamic logic is more commonly and preferably referred to as clocked logic, as it makes clear the distinction between this type of design and static logic, as will be explained in the next section. Unfortunately, the term dynamic logic is also used in the context of artificial intelligence to describe something entirely different. These two uses of the term are unrelated.

To additionally confuse the matter, clocked logic is sometimes used as a synonym for sequential logic; this usage is nonstandard and should be avoided.

In this article, dynamic logic is used.

The largest difference between static and dynamic logic is that in dynamic logic, a clock signal is used to evaluate combinational logic. However, to truly comprehend the importance of this distinction, the reader will need some background on static logic.

In most types of logic design, termed static logic, there is at all times some mechanism to drive the output either high or low. In many of the popular logic styles, such as TTL and traditional CMOS, this principle can be rephrased as a statement that there is always a low-impedance path between the output and either the supply voltage or the ground. As a sidenote, there is of course an exception in this definition in the case of high impedance outputs, such as a tri-state buffer; however, even in these cases, the circuit is intended to be used within a larger system where some mechanism will drive the output, and they do not qualify as distinct from static logic.

In contrast, in dynamic logic, there is not always a mechanism driving the output high or low. In the most common version of this concept, the output is driven high or low during distinct parts of the clock cycle.

As an example, consider first the static logic implementation of a NAND gate (here in CMOS):

This circuit implements the logic function

- $out\; =\; overline\{AB\}$

Consider now a dynamic logic implementation:

The dynamic logic circuit requires two phases. The first phase, when Clock is low, is called the setup phase or the precharge phase and the second phase, when Clock is high, is called the evaluation phase. In the setup phase, the output is driven high unconditionally (no matter the values of the inputs A and B). The capacitor, which represents the load capacitance of this gate, becomes charged. Because the transistor at the bottom is turned off, it is impossible for the output to be driven low during this phase.

During the evaluation phase, Clock is high. If A and B are also high, the output will be pulled low. Otherwise, the output stays high (due to the load capacitance).

Dynamic logic has a few potential problems that static logic does not. For example, if the clock speed is too slow, the output will decay too quickly to be of use.

A popular implementation is domino logic.

- Introduction to CMOS VLSI Design – Lecture 9: Circuit Families – David Harris' lecture notes on the subject.

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Last updated on Sunday October 05, 2008 at 03:58:06 PDT (GMT -0700)

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This article is licensed under the GNU Free Documentation License.

Last updated on Sunday October 05, 2008 at 03:58:06 PDT (GMT -0700)

View this article at Wikipedia.org - Edit this article at Wikipedia.org - Donate to the Wikimedia Foundation

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