Originally, CSP was the acronym for Chip Size Packaging. As only a few packages are chip size, the meaning of the acronym was adapted to Chip Scale Packaging. According to IPC’s standard J-STD-012, "Implementation of Flip Chip and Chip Scale Technology", in order to qualify as chip scale, the package must have an area no greater than 1.2 times that of the die and it must be a single-die, direct surface mountable package. Another criterion that is often applied to qualify these packages as CSPs is that their ball pitch should be no more than 1 mm.
The die may be mounted on an interposer upon which pads or balls are formed, as in flip chip ball grid array (BGA) packaging, or the pads may be etched or printed directly onto the silicon wafer, resulting in a package very close to the size of the silicon die: such a package is called a wafer level chip scale package (WL-CSP) or a wafer level package (WLP).
Chip scale packages can be classified into the following groups: 1. Customized Leadframe based CSP 2. Flexible substrate based CSP 3. Rigid substrate based CSP and 4. Wafer-Level redistribution CSP (WL-CSP)
CPLDs move to chip scale packaging: compact devices make low-power applications possible for portable products.(PACKAGING)(Brief Article)
Nov 22, 2004; Consumer demand for small equipment with long battery life seems unquenchable, so the need for compact, low-power devices...