Blackfin

Blackfin

[blak-fin]

Blackfin refers to a family of 16/32-bit microprocessors with built-in Digital Signal Processor (DSP) functionality, which is traditionally only accompanied by a small and power-efficient microcontroller. The result is a low-power, unified processor architecture that can run operating systems while simultaneously handling complex numeric tasks such as real-time H.264 video encoding.

The processors come in several varieties of hardware development kits and a community supported Linux port is available. Currently the microprocessor is manufactured by Analog Devices.

Architecture Details

Blackfin processors use a 32-bit RISC MCU programming model on a SIMD architecture, which was co-developed by Intel and Analog Devices, as MSA (Micro Signal Architecture).

The Blackfin processor architecture was announced in December, 2000 and first demonstrated at the Embedded Systems Conference in June, 2001.

The Blackfin architecture incorporates aspects of ADI's older SHARC architecture and Intel's Xscale architecture into a single core, combining Digital Signal Processing (DSP) and micro-controller functionality. There are many differences in the core architecture between Blackfin/MSA and Xscale/ARM or SHARC, but the combination provides improvements in performance, programmability and power consumption over traditional DSP or RISC architecture designs.

The Blackfin architecture encompasses various different CPU models, each targeting particular applications. Analog Devices keeps a comprehensive list of products The Blackfin family is summarized in the following table.

Processor
ADSP-
Max. Clock
(MHz)
Cores Instr L1 SRAM/
(Cache)
(KB)
Data L1 SRAM/
(Cache)
scratch
(KB)
L2 SRAM
(KB)
On-
chip
Flash
Host Port Code Security Ether-
net
MAC
SD/
SDIO
16-bit PPIs 18/24-bit PPIs SDRAM USB ATAPI CAN I²C (TWI) SPI UART SPORT GPIO MXVR
BF5221 600 1 64 (16) 64 (32)
4
- - Yes Yes - - 1 0 SDR
x16
- - - 1 1 2 2 48 pins -
BF5251 600 1 64 (16) 64 (32)
4
- - Yes Yes - - 1 0 SDR
x16
2.0
OTG
- - 1 1 2 2 48 pins -
BF5271 600 1 64 (16) 64 (32)
4
- - Yes Yes 1 - 1 0 SDR
x16
2.0
OTG
- - 1 1 2 2 48 pins -
BF542 600 1 64 (16) 64 (32)
4
- - - Yes - 1 1 0 DDR
x16
1 1 1 1 2 3 3 152 pins -
BF544 533 1 64 (16) 64 (32)
4
64 - Yes Yes - - 1 1 DDR
x16
- - 2 2 2 3 3 152 pins -
BF548 600 1 64 (16) 64 (32)
4
128 - Yes Yes - 1 1 1 DDR
x16
2.0
OTG
1 2 2 3 4 4 152 pins -
BF549 533 1 64 (16) 64 (32)
4
128 - Yes Yes - 1 1 1 DDR
x16
2.0
OTG
1 2 2 3 4 4 152 pins 1
BF531 400 1 32 (16) 16 (16)
4
- - - - - - 1 - SDR
x16
- - - - 1 1 2 16 -
BF532 400 1 48 (16) 32 (32)
4
- - - - - - 1 - SDR
x16
- - - - 1 1 2 16 -
BF533 600 1 80 (16) 64 (32)
4
- - - - - - 1 - SDR
x16
- - - - 1 1 2 16 -
BF534 500 1 64 (16) 64 (32)
4
- - - - - - 1 - SDR
x16
- - 1 1 1 1 2 48 -
BF536 500 1 64 (16) 32 (32)
4
- - - - 1 - 1 - SDR
x16
- - 1 1 1 1 2 48 -
BF537 600 1 64 (16) 64 (32)
4
- - - - 1 - 1 - SDR
x16
- - 1 1 1 2 2 48 -
BF538 500 1 80 (16) 64 (32)
4
- - - - - - 1 - SDR
x16
- - 1 2 3 3 4 54 -
BF538F 500 1 80 (16) 64 (32)
4
- 512
1024
- - - - 1 - SDR
x16
- - 1 2 3 3 4 54 -
BF539 500 1 80 (16) 64 (32)
4
- - - - - - 1 - SDR
x16
- - 1 2 3 3 4 38 1
BF539F 500 1 80 (16) 64 (32)
4
- 512
1024
- - - - 1 - SDR
x16
- - 1 2 3 3 4 38 1
BF561 600 2 64 (16)
per core
64 (32)
4
per core
128 - - - - - 2 - SDR
x32
- - - - 1 1 2 48 -
BF535 350 1 16 32
4
256 - - - - - - - SDR
x16
1.1 - - - 2 2 2 16 -

1 The BF52xC family includes an embedded 48 kHz, stereo audio CODEC (2xADCs, 2xDACs).

In addition to the features in the table above, all Blackfin processors have the following peripherals

  • Debug/JTAG Interface for in-system debugging
  • Real-time clock
  • Internal core voltage switching regulator
  • Watchdog timer
  • Timers/PWM outputs/PWM capture ports
  • Core timer (runs at core clock speed)

Architecture Features

Core Features

What is regarded as the Blackfin "core" is contextually dependent.

  • For some applications, the DSP is central. It combines two 16-bit hardware MACs, two 40-bit ALUs, and a 40-bit barrel shifter. This allows the processor to execute up to three instructions per clock cycle, depending on the level of optimization performed by the compiler and/or programmer.
  • Other applications emphasize the RISC core. It includes memory protection, different operating modes (user, kernel), single-cycle opcodes, data and instruction caches, and instructions for bit test, byte, word, or integer accesses and a variety of on-chip peripherals.

The ISA also features a high level of expressiveness, allowing the assembly programmer (or compiler) to highly optimize an algorithm to the hardware features present.

Memory and DMA

The Blackfin uses a byte-addressable, flat memory map. Internal L1 memory, internal L2 memory, external memory and all memory-mapped control registers all reside in this 32-bit address space, so that from a programming point-of-view, the Blackfin has a Von Neumann architecture.

The L1 internal SRAM memory, which runs at the core-clock speed of the device, is based on a Harvard Architecture. Instruction memory and data memory are independent and connect to the core via dedicated memory buses which allows for high sustained data rates between the core and L1 memory.

Portions of instruction and data L1 SRAM can be optionally configured as cache (independently).

Certain Blackfin processors also have between 64KB and 256KB of L2 memory. This memory runs slower than the core clock speed. Code and data can be mixed in L2.

Blackfin processors support a variety of external memories including SDRAM, DDR-SDRAM, NOR FLASH, NAND FLASH and SRAM. Some Blackfin also include mass-storage interfaces such as ATAPI, and SD/SDIO. They can support hundreds of megabytes of memory in the external memory space.

Coupled with the significant core and memory system is a DMA engine that can operate between any of its peripherals and main (or external) memory. The processors typically have a dedicated DMA channel for each peripheral, which enables very high throughput for applications that can take advantage of it such as real-time standard-definition (D1) video encoding and decoding.

Micro-controller Features

The Blackfin architecture contains a number of attributes commonly found on microprocessors and micro-controllers. These features allow Blackfin to efficiently and securely run many commercial and open-source operating systems.

  • Memory Protection Unit : All Blackfin processors contain a Memory Protection Unit (MPU). The MPU provides protection and caching strategies across the entire memory space. The MPU allows Blackfin to support many full-featured operating systems, RTOSs and kernels like ThreadX, µC/OS-II, or (noMMU) Linux. The Blackfin MPU does not provide address translation like a traditional Memory Management Unit (MMU) thus it does not support virtual memory or separate memory addresses per process. This is why Blackfin currently can not support operating systems requiring virtual memory such as WinCE or QNX. Confusingly, in most of the Blackfin documentation, the MPU is referred to as a MMU.
  • User/Supervisor Modes : Blackfin supports three run-time modes : supervisor, user and emulation. In supervisor mode, all processor resources are accessible from the running process. However, when in user mode, system resources and regions of memory can be protected (with the help of the MPU). In a modern operating system or RTOS, the kernel typically runs in supervisor mode and threads/processes will run in user mode. If a thread crashes or attempts to access a protected resource (memory, peripheral, etc) an exception will be thrown and the kernel will then be able to shut down the offending thread/process.
  • Variable-Length, RISC-Like Instruction Set : Blackfin supports 16, 32 and 64-bit instructions. Commonly-used control instructions are encoded as 16-bit opcodes while complex DSP and mathematically intensive functions are encoded as 32 and 64-bit opcodes. This variable length opcode encoding allows Blackfin to achieve good code density equivalent to modern micro-processor architectures.

Media Processing Features

The Blackfin instruction set contains media processing extensions to help accelerate pixel processing operations commonly used in video compression and image compression and decompression algorithms.

Peripherals

Blackfin processors contain a wide array of connectivity peripherals.

  • USB 2.0 OTG (On-The-Go)
  • ATAPI
  • MXVR : a MOST (Media Oriented Systems Transport) Network Interface Controller. MOST is a registered trademark of SMSC.
  • PPI (Parallel Peripheral Interface) : A parallel input/output port that can be used to connect to LCDs, video encoders (video DACs), video decoders (video ADCs), CMOS sensors, CCDs and generic, parallel, high-speed devices. The PPI can run up to 65 MHz and can be configured from 8 to 16-bits wide.
  • SPORT : A synchronous, high speed serial port that can support TDM, I2S and a number of other configurable framing modes for connection to ADCs, DACs, other processors, FPGAs, etc.
  • CAN : A wide-area, low-speed serial bus that is fairly popular in automotive and industrial electronics.
  • UART (Universal Asynchronous Receiver Transmitter) : allows for bi-directional communication with RS232 devices (PCs, modems, PC peripherals, etc), MIDI devices, IRDA devices.
  • SPI : A fast serial bus used in many high-speed embedded electronics applications.
  • I²C (also known as TWI (two-wire interface)) : A lower speed, shared serial bus.

Because all of the peripheral control registers are memory-mapped in the normal address space, they are quite easy to set-up.

Development Tools Software

ADI provides its own software development toolchain, CROSSCORE (VisualDSP++), but other options are also available, such as Green Hills Software's MULTI IDE, the GNU GCC Toolchain for the Blackfin processor family, or National Instruments' LabVIEW Embedded Module.

Supported Operating Systems, RTOSs & Kernels

Blackfin supports numerous commercial and open-source operating systems.

OS/RTOS/Kernels on Blackfin
Title Type Comments
Linux Free Software GPL Integrated into mainline kernel, distributed as part of the µClinux Distribution
ThreadX Commercial
Nucleus Commercial
Fusion RTOS Commercial
µC/OS-II Commercial/Source Available
velOSity Microkernel Commercial
INTEGRITY Commercial
RTEMS Open-Source/GPL
T2 SDE Open-Source/GPL
VDK Commercial ADI's real-time kernel. Ships with VisualDSP++.
TOPPERS/JSP Open-Source

See also

External links

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