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Computer in which continuously variable physical quantities, such as electrical potential, fluid pressure, or mechanical motion, are used to represent (analogously) the quantities in the problem to be solved. The analog system is set up according to initial conditions and then allowed to change freely. Answers to the problem are obtained by measuring the variables in the analog model. Analog computers are especially well suited to simulating dynamic systems; such simulations may be conducted in real time or at greatly accelerated rates, allowing experimentation by performing many runs with different variables. They have been widely used in simulating the operation of aircraft, nuclear power plants, and industrial chemical processes. *Seealso* digital computer.

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Encyclopedia Britannica, 2008. Encyclopedia Britannica Online.

An analog-to-digital converter (abbreviated ADC, A/D or A to D) is an electronic integrated circuit, which converts continuous signals to discrete digital numbers. The reverse operation is performed by a digital-to-analog converter (DAC).

Typically, an ADC is an electronic device that converts an input analog voltage (or current) to a digital number. The digital output may be using different coding schemes, such as binary, Gray code or two's complement binary. However, some non-electronic or only partially electronic devices, such as rotary encoders, can also be considered ADCs.

Resolution can also be defined electrically, and expressed in volts. The voltage resolution of an ADC is equal to its overall voltage measurement range divided by the number of discrete intervals as in the formula:

$Q\; =\; dfrac\{E\_\{FSR\}\}\{2^M\}\; =\; dfrac\{E\_\{FSR\}\}N$

Where:

- Q is resolution in volts per step (volts per output code),

- E
_{FSR}is the full scale voltage range = $V\_\{RefHi\}\; -\; V\_\{RefLo\}$ and

- M is the ADC's resolution in bits.

The number of intervals is given by the number of available levels (output codes), which is: $N\; =\{2^M\}$

Some examples may help:

- Example 1
- Full scale measurement range = 0 to 10 volts
- ADC resolution is 12 bits: 2
^{12}= 4096 quantization levels (codes) - ADC voltage resolution is: (10V - 0V) / 4096 codes = 10V / 4096 codes $approx$ 0.00244 volts/code $approx$ 2.44 mV/code
- Example 2
- Full scale measurement range = -10 to +10 volts
- ADC resolution is 14 bits: 2
^{14}= 16384 quantization levels (codes) - ADC voltage resolution is: (10V - (-10V)) / 16384 codes = 20V / 16384 codes $approx$ 0.00122 volts/code $approx$ 1.22 mV/code
- Example 3
- Full scale measurement range = 0 to 8 volts
- ADC resolution is 3 bits: 2
^{3}= 8 quantization levels (codes) - ADC voltage resolution is: (8 V − 0 V)/8 codes = 8 V/8 codes = 1 volts/code = 1000 mV/code

In practice, the smallest output code ("0" in an unsigned system) represents a voltage range which is 0.5X (half-wide) of the ADC voltage resolution (Q) while the largest output code represents a voltage range which is 1.5X (50% wider) of the ADC voltage resolution. The other N − 2 codes are all equal in width and represent the ADC voltage resolution (Q) calculated above. Doing this centers the code on an input voltage that represents the Mth division of the input voltage range. For example, in Example 3, with the 3-bit ADC spanning an 8 V range, each of the N divisions would represent 1 V, except the 1st ("0" code) which is 0.5 V wide, and the last ("7" code) which is 1.5 V wide. Doing this the "1" code spans a voltage range from 0.5 to 1.5 V, the "2" code spans a voltage range from 1.5 to 2.5 V, etc. Thus, if the input signal is at 3/8ths of the full-scale voltage, then the ADC outputs the "3" code, and will do so as long as the voltage stays within the range of 2.5/8ths and 3.5/8ths. This practice is called "Mid-Tread" operation. This type of ADC can be modeled mathematically as:

$ADC\_\{Code\}\; =\; ROUND((dfrac\{2^M\}\; \{V\_\{RefHi\}\; -\; V\_\{RefLo\}\})\; *\; (V\_\{In\}-V\_\{RefLo\})\; ).$

The exception to this convention seems to be the Microchip PIC processor, where all M steps are equal width. This practice is called "Mid-Rise with Offset" operation.

$ADC\_\{Code\}\; =\; FLOOR((dfrac\{2^M\}\; \{V\_\{RefHi\}\; -\; V\_\{RefLo\}\})\; *\; (V\_\{In\}-V\_\{RefLo\})\; )$

In practice, the useful resolution of the converter is limited by the signal-to-noise ratio of the signal in question. If there is too much noise present in the analog input, it will be impossible to accurately resolve beyond a certain number of bits of resolution, the "effective number of bits" (ENOB). If a preamplifier has been used prior to A/D conversion, the noise introduced by the amplifier is an important contributing factor towards the overall SNR. While the ADC will produce a result, the result is not accurate, since its lower bits are simply measuring noise. The signal-to-noise ratio should be around 6 dB per bit of resolution required.

- m(k + b)

to

- m(k + 1 + b),

where m and b are constants. Here b is typically 0 or −0.5. When b = 0, the ADC is referred to as mid-rise, and when b = −0.5 it is referred to as mid-tread.

This is the same principle behind the companders used in some tape-recorders and other communication systems, and is related to entropy maximization. (Never confuse companders with compressors!)

For example, a voice signal has a Laplacian distribution. This means that the region around the lowest levels, near 0, carries more information than the regions with higher amplitudes. Because of this, logarithmic ADCs are very common in voice communication systems to increase the dynamic range of the representable values while retaining fine-granular fidelity in the low-amplitude region.

An eight-bit a-law or the μ-law logarithmic ADC covers the wide dynamic range and has a high resolution in the critical low-amplitude region, that would otherwise require a 12-bit linear ADC.

These errors are measured in a unit called the LSB, which is an abbreviation for least significant bit. In the above example of an eight-bit ADC, an error of one LSB is 1/256 of the full signal range, or about 0.4%.

Quantization error is due to the finite resolution of the ADC, and is an unavoidable imperfection in all types of ADC. The magnitude of the quantization error at the sampling instant is between zero and half of one LSB.

In the general case, the original signal is much larger than one LSB. When this happens, the quantization error is not correlated with the signal, and has a uniform distribution. Its RMS value is the standard deviation of this distribution, given by $\{1\; over\; \{sqrt\{12\}\}\}\; mathrm\{LSB\}\; approx\; 0.289\; mathrm\{LSB\}$. In the eight-bit ADC example, this represents 0.113% of the full signal range.

At lower levels the quantizing error becomes dependent of the input signal, resulting in distortion. This distortion is created after the anti-aliasing filter, and if these distortions are above 1/2 the sample rate they will alias back into the audio band. In order to make the quantizing error independent of the input signal, noise with an amplitude of 1 quantization step is added to the signal. This slightly reduces signal to noise ratio, but completely eliminates the distortion. It is known as dither.

All ADCs suffer from non-linearity errors caused by their physical imperfections, causing their output to deviate from a linear function (or some other function, in the case of a deliberately non-linear ADC) of their input. These errors can sometimes be mitigated by calibration, or prevented by testing.

Important parameters for linearity are integral non-linearity (INL) and differential non-linearity (DNL).

One can see that the error is relatively small at low frequencies, but can become significant at high frequencies.

This effect can be ignored if it is relatively small as compared with quantizing error. Jitter requirements can be calculated using the following formula: $Delta\; t\; <\; frac\{1\}\{2^q\; pi\; f\_0\}$, where q is a number of ADC bits.

ADC resolution in bit | input frequency | ||||||
---|---|---|---|---|---|---|---|

1 Hz | 44.1 kHz | 192 kHz | 1 MHz | 10 MHz | 100 MHz | 1 GHz | |

8 | 1243 µs | 28.2 ns | 6.48 ns | 1.24 ns | 124 ps | 12.4 ps | 1.24 ps |

10 | 311 µs | 7.05 ns | 1.62 ns | 311 ps | 31.1 ps | 3.11 ps | 0.31 ps |

12 | 77.7 µs | 1.76 ns | 405 ps | 77.7 ps | 7.77 ps | 0.78 ps | 0.08 ps |

14 | 19.4 µs | 441 ps | 101 ps | 19.4 ps | 1.94 ps | 0.19 ps | 0.02 ps |

16 | 4.86 µs | 110 ps | 25.3 ps | 4.86 ps | 0.49 ps | 0.05 ps | – |

18 | 1.21 µs | 27.5 ps | 6.32 ps | 1.21 ps | 0.12 ps | – | – |

20 | 304 ns | 6.88 ps | 1.58 ps | 0.16 ps | – | – | – |

24 | 19.0 ns | 0.43 ps | 0.10 ps | – | – | – | – |

32 | 74.1 ps | – | – | – | – | – | – |

A continuously varying bandlimited signal can be sampled (that is, the signal values at intervals of time T, the sampling time, are measured and stored) and then the original signal can be exactly reproduced from the discrete-time values by an interpolation formula. The accuracy is limited by quantization error. However, this faithful reproduction is only possible if the sampling rate is higher than twice the highest frequency of the signal. This is essentially what is embodied in the Shannon-Nyquist sampling theorem.

Since a practical ADC cannot make an instantaneous conversion, the input value must necessarily be held constant during the time that the converter performs a conversion (called the conversion time). An input circuit called a sample and hold performs this task—in most cases by using a capacitor to store the analogue voltage at the input, and using an electronic switch or gate to disconnect the capacitor from the input. Many ADC integrated circuits include the sample and hold subsystem internally.

If the digital values produced by the ADC are, at some later stage in the system, converted back to analog values by a digital to analog converter or DAC, it is desirable that the output of the DAC be a faithful representation of the original signal. If the input signal is changing much faster than the sample rate, then this will not be the case, and spurious signals called aliases will be produced at the output of the DAC. The frequency of the aliased signal is the difference between the signal frequency and the sampling rate. For example, a 2 kHz sinewave being sampled at 1.5 kHz would be reconstructed as a 500 Hz sinewave. This problem is called aliasing.

To avoid aliasing, the input to an ADC must be low-pass filtered to remove frequencies above half the sampling rate. This filter is called an anti-aliasing filter, and is essential for a practical ADC system that is applied to analog signals with higher frequency content.

Although aliasing in most systems is unwanted, it should also be noted that it can be exploited to provide simultaneous down-mixing of a band-limited high frequency signal (see frequency mixer).

An audio signal of very low level (with respect to the bit depth of the ADC) sampled without dither sounds extremely distorted and unpleasant. Without dither the low level always yields a '1' from the A to D. With dithering, the true level of the audio is still recorded as a series of values over time, rather than a series of separate bits at one instant in time.

A virtually identical process, also called dither or dithering, is often used when quantizing photographic images to a fewer number of bits per pixel—the image becomes noisier but to the eye looks far more realistic than the quantized image, which otherwise becomes banded. This analogous process may help to visualize the effect of dither on an analogue audio signal that is converted to digital.

Dithering is also used in integrating systems such as electricity meters. Since the values are added together, the dithering produces results that are more exact than the LSB of the analog-to-digital converter.

Note that dither can only increase the resolution of a sampler, it cannot improve the linearity, and thus accuracy does not necessarily improve.

- digital filters can have better properties (sharper rolloff, phase) than analogue filters, so a sharper anti-aliasing filter can be realised and then the signal can be downsampled giving a better result
- a 20 bit ADC can be made to act as a 24 bit ADC with 256x oversampling
- the signal-to-noise ratio due to quantization noise will be higher than if the whole available band had been used. With this technique, it is possible to obtain an effective resolution larger than that provided by the converter alone

- A direct conversion ADC or flash ADC has a bank of comparators, each firing for their decoded voltage range. The comparator bank feeds a logic circuit that generates a code for each voltage range. Direct conversion is very fast, but usually has only 8 bits of resolution (255 comparators - since the number of comparators required is 2
^{n}- 1) or fewer, as it needs a large, expensive circuit. ADCs of this type have a large die size, a high input capacitance, and are prone to produce glitches on the output (by outputting an out-of-sequence code). Scaling to newer submicron technologies does not help as the device mismatch is the dominant design limitation. They are often used for video, wideband communications or other fast signals in optical storage. - A successive-approximation ADC uses a comparator to reject ranges of voltages, eventually settling on a final voltage range. Successive approximation works by constantly comparing the input voltage to the output of an internal digital to analog converter (DAC, fed by the current value of the approximation) until the best approximation is achieved. At each step in this process, a binary value of the approximation is stored in a successive approximation register (SAR). The SAR uses a reference voltage (which is the largest signal the ADC is to convert) for comparisons. For example if the input voltage is 60 V and the reference voltage is 100 V, in the 1st clock cycle, 60 V is compared to 50 V (the reference, divided by two. This is the voltage at the output of the internal DAC when the input is a '1' followed by zeros), and the voltage from the comparator is positive (or '1') (because 60 V is greater than 50 V). At this point the first binary digit (MSB) is set to a '1'. In the 2nd clock cycle the input voltage is compared to 75 V (being halfway between 100 and 50 V: This is the output of the internal DAC when its input is '11' followed by zeros) because 60 V is less than 75 V, the comparator output is now negative (or '0'). The second binary digit is therefore set to a '0'. In the 3rd clock cycle, the input voltage is compared with 62.5 V (halfway between 50 V and 75 V: This is the output of the internal DAC when its input is '101' followed by zeros). The output of the comparator is negative or '0' (because 60 V is less than 62.5 V) so the third binary digit is set to a 0. The fourth clock cycle similarly results in the fourth digit being a '1' (60 V is greater than 56.25 V, the DAC output for '1001' followed by zeros). The result of this would be in the binary form 1001. This is also called bit-weighting conversion, and is similar to a binary search. The analogue value is rounded to the nearest binary value below, meaning this converter type is mid-rise (see above). Because the approximations are successive (not simultaneous), the conversion takes one clock-cycle for each bit of resolution desired. The clock frequency must be equal to the sampling frequency multiplied by the number of bits of resolution desired. For example, to sample audio at 44.1 kHz with 32 bit resolution, a clock frequency of over 1.4 MHz would be required. ADCs of this type have good resolutions and quite wide ranges. They are more complex than some other designs.
- A ramp-compare ADC (also called integrating, dual-slope or multi-slope ADC) produces a saw-tooth signal that ramps up, then quickly falls to zero. When the ramp starts, a timer starts counting. When the ramp voltage matches the input, a comparator fires, and the timer's value is recorded. Timed ramp converters require the least number of transistors. The ramp time is sensitive to temperature because the circuit generating the ramp is often just some simple oscillator. There are two solutions: use a clocked counter driving a DAC and then use the comparator to preserve the counter's value, or calibrate the timed ramp. A special advantage of the ramp-compare system is that comparing a second signal just requires another comparator, and another register to store the voltage value. A very simple (non-linear) ramp-converter can be implemented with a microcontroller and one resistor and capacitor. Vice versa a filled capacitor can be taken from an integrator, time-to-amplitude converter, phase detector, sample and hold circuit, or peak and hold circuit and discharged. This has the advantage that a slow comparator cannot be disturbed by fast input changes.
- A delta-encoded ADC has an up-down counter that feeds a digital to analog converter (DAC). The input signal and the DAC both go to a comparator. The comparator controls the counter. The circuit uses negative feedback from the comparator to adjust the counter until the DAC's output is close enough to the input signal. The number is read from the counter. Delta converters have very wide ranges, and high resolution, but the conversion time is dependent on the input signal level, though it will always have a guaranteed worst-case. Delta converters are often very good choices to read real-world signals. Most signals from physical systems do not change abruptly. Some converters combine the delta and successive approximation approaches; this works especially well when high frequencies are known to be small in magnitude.
- A pipeline ADC (also called subranging quantizer) uses two or more steps of subranging. First, a coarse conversion is done. In a second step, the difference to the input signal is determined with a digital to analog converter (DAC). This difference is then converted finer, and the results are combined in a last step. This can be considered a refinement of the successive approximation ADC wherein the feedback reference signal consists of the interim conversion of a whole range of bits (for example, four bits) rather than just the next-most-significant bit. By combining the merits of the successive approximation and flash ADCs this type is fast, has a high resolution, and only requires a small die size.
- A Sigma-Delta ADC (also known as a Delta-Sigma ADC) oversamples the desired signal by a large factor and filters the desired signal band. Generally a smaller number of bits than required are converted using a Flash ADC after the Filter. The resulting signal, along with the error generated by the discrete levels of the Flash, is fed back and subtracted from the input to the filter. This negative feedback has the effect of noise shaping the error due to the Flash so that it does not appear in the desired signal frequencies. A digital filter (decimation filter) follows the ADC which reduces the sampling rate, filters off unwanted noise signal and increases the resolution of the output. (sigma-delta modulation, also called delta-sigma modulation)

Nonelectronic ADCs usually use some scheme similar to one of the above.

Most converters sample with 6 to 24 bits of resolution, and produce fewer than 1 megasample per second. It is rare to get more than 24 bits of resolution because of thermal noise generated by passive components such as resistors. For audio applications and in room temperatures, such noise is usually a little less than 1 μV (microvolt) of white noise. If the Most Significant Bit corresponds to a standard 2 volts of output signal, this translates to a noise-limited performance that is less than 20~21 bits, and obviates the need for any dithering. Mega- and gigasample converters are available, though (Feb 2002). Megasample converters are required in digital video cameras, video capture cards, and TV tuner cards to convert full-speed analog video to digital video files. Commercial converters usually have ±0.5 to ±1.5 LSB error in their output.

In many cases the most expensive part of an integrated circuit is the pins, because they make the package larger, and each pin has to be connected to the integrated circuit's silicon. To save pins, it's common for slow ADCs to send their data one bit at a time over a serial interface to the computer, with the next bit coming out when a clock signal changes state, say from zero to 5V. This saves quite a few pins on the ADC package, and in many cases, does not make the overall design any more complex. (Even microprocessors which use memory-mapped IO only need a few bits of a port to implement a serial bus to an ADC.)

Commercial ADCs often have several inputs that feed the same converter, usually through an analog multiplexer. Different models of ADC may include sample and hold circuits, instrumentation amplifiers or differential inputs, where the quantity measured is the difference between two voltages.

ADCs are integral to current music reproduction technology. Since much music production is done on computers, when an analog recording is used, an ADC is needed to create the PCM data stream that goes onto a compact disc.

The current crop of AD converters utilized in music can sample at rates up to 192 kilohertz. Many people in the business consider this an overkill and pure marketing hype, due to the Nyquist-Shannon sampling theorem. Simply put, they say the analog waveform does not have enough information in it to necessitate such high sampling rates, and typical recording techniques for high-fidelity audio are usually sampled at either 44.1 kHz (the standard for CD) or 48 kHz (commonly used for radio/TV broadcast applications). However, this kind of bandwidth headroom allows the use of cheaper or faster anti-aliasing filters of less severe filtering slopes. The proponents of oversampling assert that such shallower anti-aliasing filters produce less deleterious effects on sound quality, exactly because of their gentler slopes. Others prefer entirely filterless AD conversion, arguing that aliasing is less detrimental to sound perception than pre-conversion brickwall filtering. Considerable literature exists on these matters, but commercial considerations often play a significant role. Most high-profile recording studios record in 24-bit/192-176.4 kHz PCM or in DSD formats, and then downsample or decimate the signal for Red-Book CD production.

- Digital signal processing
- Digital-to-analog converter
- Digital-to-digital converter
- quantization (signal processing)
- quantization noise
- Modem
- Differential linearity

- "Understanding analog to digital converter specifications" article by Len Staller 2005-02-24.
- S. Norsworthy, R. Schreier, G. Temes, Delta-Sigma Data Converters. ISBN 0-7803-1045-4.
- Mingliang Liu, Demystifying Switched-Capacitor Circuits. ISBN 0-7506-7907-7.
- Behzad Razavi, Principles of Data Conversion System Design. ISBN 0-7803-1093-4.
- David Johns, Ken Martin, Analog Integrated Circuit Design. ISBN 0-471-14448-7.
- Phillip E. Allen, Douglas R. Holberg, CMOS Analog Circuit Design. ISBN 0-19-511644-5.
- Walt Kester, "The Data Conversion Handbook". ISBN 0-7506-7841-0.

- Learning by Simulations A simulation showing the effects of sampling frequency and ADC resolution.
- ADC using the Parallel Port and NE555 timer
- Counting Type ADC A simple tutorial showing how to build your first ADC.
- An Introduction to Delta Sigma Converters A very nice overview of Delta-Sigma converter theory.
- Freescale Application Note AN2438 ADC Definitions and Specifications
- Analog Sampling Basics article by National Instruments
- Using the Analog to Digital Converter AppNote by MicroChip Semi
- Digital Dynamic Analysis of A/D Conversion Systems through Evaluation Software based on FFT/DFT Analysis RF Expo East, 1987
- Which ADC Architecture Is Right for Your Application? article by Walt Kester
- Interfacing ADC 0808 to 8051 Micro Controller

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Last updated on Thursday October 09, 2008 at 09:15:56 PDT (GMT -0700)

View this article at Wikipedia.org - Edit this article at Wikipedia.org - Donate to the Wikimedia Foundation

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