Structure

Header section

The header section of the VCD file includes a timestamp, a simulator version number, and a timescale, which maps the time increments listed in the value change section to simulation time units.

Variable definition section

The variable definition section of the VCD file contains scope information as well as lists of signals instantiated in a given scope. Each variable is assigned an arbitrary, compact ASCII identifier for use in the value change section. The scope type definitions closely follow Verilog concepts, and include the types module, task, function, and fork.

Value change section

The value change section contains a series of time-ordered value changes for the signals in a given simulation model.

Syntax

Example:

$timescale 1 ns $end

Another example of a file is:

$timescale 1ps $end

$scope module logic $end

$var wire 8 # data $end

$var wire 1 $ data_valid $end

$var wire 1 % en $end

$var wire 1 & rx_en $end

$var wire 1 ' tx_en $end

$var wire 1 (empty $end

$var wire 1 ) underrun $end

$upscope $end

$enddefinitions $end

#0

b10000001 #

0$

1%

0&

1'

0(

0)

#2211

0'

#2296

b0 #

1$

#2302

0$

#2303

The code above defines 7 signals by using $var:

$var type bitwidth id name

The id is used later on the wave description, the wave description starts after $enddefinitions $end, and is base on timestamps, starting with #. On each timestamp specified the list of signals that their value were modified. This is done by the pair:

new_value id

notice a white space is not separating between them.

All VCD tokens are delineated by whitespace.

See also

• Waveform viewer

External links

• IEEE Std 1364-2001 – The official standard for Verilog 2001 (not free).