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TEST (x86 instruction)&o=10616
X86 instruction listings
The x86 instruction set has undergone numerous changes over time. Most of them were to add new functionality to the instruction set.
x86 integer instructions
This is the full 8086/8088 instruction set, but most, if not all of these instructions are available in 32-bit mode, they just operate on 32-bit registers (eax, ebx, etc) and values instead of their 16-bit (ax, bx, etc) counterparts. See also x86 assembly language for a quick tutorial for this chip.Original 8086/8088 instructions
| Instruction | Meaning | Notes |
|---|---|---|
| AAA | ASCII adjust AL after addition | used with unpacked binary coded decimal |
| AAD | ASCII adjust AX before division | buggy in the original instruction set, but "fixed" in the NEC V20, causing a number of incompatibilities |
| AAM | ASCII adjust AX after multiplication | |
| AAS | ASCII adjust AL after subtraction | |
| ADC | Add with carry | |
| ADD | Add | |
| AND | Logical AND | |
| CALL | Call procedure | |
| CBW | Convert byte to word | |
| CLC | Clear carry flag | |
| CLD | Clear direction flag | |
| CLI | Clear interrupt flag | |
| CMC | Complement carry flag | |
| CMP | Compare operands | |
| CMPSB | Compare bytes in memory | |
| CMPSW | Compare words | |
| CWD | Convert word to doubleword | |
| DAA | Decimal adjust AL after addition | (used with packed binary coded decimal) |
| DAS | Decimal adjust AL after subtraction | |
| DEC | Decrement by 1 | |
| DIV | Unsigned divide | |
| ESC | Used with floating-point unit | |
| HLT | Enter halt state | |
| IDIV | Signed divide | |
| IMUL | Signed multiply | |
| IN | Input from port | |
| INC | Increment by 1 | |
| INT | Call to interrupt | |
| INTO | Call to interrupt if overflow | |
| IRET | Return from interrupt | |
| Jxx | Jump if condition | (JA, JAE, JB, JBE, JC, JCXZ, JE, JG, JGE, JL, JLE, JNA, JNAE, JNB, JNBE, JNC, JNE, JNG, JNGE, JNL, JNLE, JNO, JNP, JNS, JNZ, JO, JP, JPE, JPO, JS, JZ) |
| JMP | Jump | |
| LAHF | Load flags into AH register | |
| LDS | Load pointer using DS | |
| LEA | Load Effective Address | |
| LES | Load ES with pointer | |
| LOCK | Assert BUS LOCK# signal | (for multiprocessing) |
| LODSB | Load byte | |
| LODSW | Load word | |
| LOOP/LOOPx | Loop control | (LOOPE, LOOPNE, LOOPNZ, LOOPZ) |
| MOV | Move | |
| MOVSB | Move byte from string to string | |
| MOVSW | Move word from string to string | |
| MUL | Unsigned multiply | |
| NEG | Two's complement negation | |
| NOP | No operation | opcode (0x90) equivalent to XCHG EAX, EAX |
| NOT | Negate the operand, logical NOT | |
| OR | Logical OR | |
| OUT | Output to port | |
| POP | Pop data from stack | (Does only work with register CS on 8086/8088.) |
| POPF | Pop data into flags register | |
| PUSH | Push data onto stack | |
| PUSHF | Push flags onto stack | |
| RCL | Rotate left (with carry) | |
| RCR | Rotate right (with carry) | |
| REPxx | Repeat CMPS/MOVS/SCAS/STOS | (REP, REPE, REPNE, REPNZ, REPZ) |
| RET | Return from procedure | |
| RETN | Return from near procedure | |
| RETF | Return from far procedure | |
| ROL | Rotate left | |
| ROR | Rotate right | |
| SAHF | Store AH into flags | |
| SAL | Shift Arithmetically left (signed shift left) | |
| SAR | Shift Arithmetically right (signed shift right) | |
| SBB | Subtraction with borrow | |
| SCASB | Compare byte string | |
| SCASW | Compare word string | |
| SHL | Shift left (unsigned shift left) | |
| SHR | Shift right (unsigned shift right) | |
| STC | Set carry flag | |
| STD | Set direction flag | |
| STI | Set interrupt flag | |
| STOSB | Store byte in string | |
| STOSW | Store word in string | |
| SUB | Subtraction | |
| TEST | Logical compare (AND) | |
| WAIT | Wait until not busy | Waits until BUSY# pin is inactive (used with floating-point unit) |
| XCHG | Exchange data | |
| XLAT | Table look-up translation | |
| XOR | Exclusive OR |
Added in specific processors
Added with 80186/80188
| Instruction | Meaning | Notes |
|---|---|---|
| BOUND | Check array index against bounds | raises software interrupt 5 if test fails |
| ENTER | Enter stack frame | equivalent to PUSH BP MOV BP, SP |
| INS | Input from port to string | equivalent to IN (E)AX, DX MOV ES:[(E)DI], (E)AX |
| LEAVE | Leave stack frame | equivalent to MOV SP, BP POP BP |
| OUTS | Output string to port | equivalent to MOV (E)AX, DS:[(E)SI] OUT DX, (E)AX |
| POPA | Pop all general purpose registers from stack | equivalent to POP DI, SI, BP, SP, BX, DX, CX, AX |
| PUSHA | Push all general purpose registers onto stack | equivalent to PUSH DI, SI, BP, SP, BX, DX, CX, AX |
Added with 80286
| Instruction | Meaning | Notes |
|---|---|---|
| ARPL | Adjust RPL field of selector | |
| CLTS | Clear task-switched flag in register CR0 | |
| LAR | Load access rights byte | |
| LGDT | Load global descriptor table | |
| LIDT | Load interrupt descriptor table | |
| LLDT | Load local descriptor table | |
| LMSW | Load machine status word | |
| LOADALL | Load all CPU registers, including internal ones such as GDT | Undocumented, (80)286 and 386 only |
| LSL | Load segment limit | |
| LTR | Load task register | |
| SGDT | Store global descriptor table | |
| SIDT | Store interrupt descriptor table | |
| SLDT | Store local descriptor table | |
| SMSW | Store machine status word | |
| STR | Store task register | |
| VERR | Verify a segment for reading | |
| VERW | Verify a segment for writing |
Added with 80386
| Instruction | Meaning | Notes |
|---|---|---|
| BSF | Bit scan forward | |
| BSR | Bit scan reverse | |
| BT | Bit test | |
| BTC | Bit test and complement | |
| BTR | Bit test and reset | |
| BTS | Bit test and set | |
| CDQ | Convert double-word to quad-word | Sign-extends EAX into EDX, forming the quad-word EDX:EAX. Since (I)DIV uses EDX:EAX as its input, CDQ must be called after setting EAX if EDX is not manually initialized (as in 64/32 division) before (I)DIV. |
| CMPSD | Compare string double-word | Compares ES:[(E)DI] with DS:[SI] |
| CWDE | Convert word to double-word | Unlike CWD, CWDE sign-extends AX to EAX instead of AX to DX:AX |
| INSB, INSW, INSD | Input from port to string with explicit size | same as INS |
| IRETx | Interrupt return; D suffix means 32-bit return, F suffix means do not generate epilogue code (i.e. LEAVE instruction) | Use IRETD rather than IRET in 32-bit situations |
| JCXZ, JECXZ | Jump if register (E)CX is zero | |
| LFS, LGS | Load far pointer | |
| LSS | Load stack segment | |
| LODSW, LODSD | Load string | can be prefixed with REP |
| LOOPW, LOOPD | Loop | Loop; counter register is (E)CX is counter |
| LOOPEW, LOOPED | Loop while equal | |
| LOOPZW, LOOPZD | Loop while zero | |
| LOOPNEW, LOOPNED | Loop while not equal | |
| LOOPNZW, LOOPNZD | Loop while not zero | |
| MOVSW, MOVSD | Move data from string to string | |
| MOVSX | Move with sign-extend | |
| MOVZX | Move with zero-extend | |
| POPAD | Pop all double-word (32-bit) registers from stack | Does not pop register ESP off of stack |
| POPFD | Pop data into EFLAGS register | |
| PUSHAD | Push all double-word (32-bit registers) onto stack | |
| PUSHFD | Push EFLAGS register onto stack | |
| SCASD | Scan string data dbouble-word | |
| SETA, SETAE, SETB, SETBE, SETC, SETE, SETG, SETGE, SETL, SETLE, SETNA, SETNAE, SETNB, SETNBE, SETNC, SETNE, SETNG, SETNGE, SETNL, SETNLE, SETNO, SETNP, SETNS, SETNZ, SETO, SETP, SETPE, SETPO, SETS, SETZ | Set byte to one on condition | |
| SHLD | Shift left double-word | |
| SHRD | Shift right double-word | |
| STOSx | Store string |
Added with 80486
| Instruction | Meaning | Notes |
|---|---|---|
| BSWAP | Byte Swap | Only works for 32 bit registers. |
| CMPXCHG | CoMPare and eXCHanGe | |
| CPUID | CPU IDentification | |
| INVD | Invalidate Internal Caches | |
| INVLPG | Invalidate TLB Entry | |
| WBINVD | Write Back and Invalidate Cache | |
| XADD | Exchange and Add |
Added with Pentium
| Instruction | Meaning | Notes |
|---|---|---|
| CMPXCHG8B | CoMPare and eXCHanGe 8 bytes | |
| RDMSR | ReaD from Model-Specific Register | |
| RDTSC | ReaD Time Stamp Counter | |
| WRMSR | WRite to Model-Specific Register |
Added with Pentium MMX
RDPMC*
Added with Pentium Pro
Conditional MOV: CMOVA, CMOVAE, CMOVB, CMOVBE, CMOVC, CMOVE, CMOVG, CMOVGE, CMOVL, CMOVLE, CMOVNA, CMOVNAE, CMOVNB, CMOVNBE, CMOVNC, CMOVNE, CMOVNG, CMOVNGE, CMOVNL, CMOVNLE, CMOVNO, CMOVNP, CMOVNS, CMOVNZ, CMOVO, CMOVP, CMOVPE, CMOVPO, CMOVS, CMOVZ, SYSENTER (SYStem call ENTER), SYSEXIT (SYStem call EXIT), RDPMC*, UD2
- RDPMC was introduced in the Pentium Pro processor and the Pentium processor with MMX technology.
Added with AMD K6-2
SYSCALL, SYSRET (functionally equivalent to SYSENTER and SYSEXIT)
Added with SSE
MASKMOVQ, MOVNTPS, MOVNTQ, PREFETCH0, PREFETCH1, PREFETCH2, PREFETCHNTA, SFENCE (for Cacheability and Memory Ordering)
Added with SSE2
CLFLUSH, LFENCE, MASKMOVDQU, MFENCE, MOVNTDQ, MOVNTI, MOVNTPD, PAUSE (for Cacheability)
Added with SSE3
LDDQU (for Video Encoding)
MONITOR, MWAIT (for thread synchronization; only on processors supporting Hyper-threading and some dual-core processors like Core 2, Phenom and others)
Added with Intel VT
VMPTRLD, VMPTRST, VMCLEAR, VMREAD, VMWRITE, VMCALL, VMLAUNCH, VMRESUME, VMXOFF, VMXON
Added with AMD-V
CLGI, SKINIT, STGI, VMLOAD, VMMCALL, VMRUN, VMSAVE (SVM instructions of AMD-V)
Added with x86-64
CMPXCHG16B (CoMPaRe and eXCHanGe 16 bytes), RDTSCP (ReaD Time Stamp Counter P?)
Added with SSE4a
LZCNT, POPCNT (POPulation CouNT) - advanced bit manipulation
x87 floating-point instructions
Original 8087 instructions
F2XM1, FABS, FADD, FADDP, FBLD, FBSTP, FCHS, FCLEX, FCOM, FCOMP, FCOMPP, FDECSTP, FDISI, FDIV, FDIVP, FDIVR, FDIVRP, FENI, FFREE, FIADD, FICOM, FICOMP, FIDIV, FIDIVR, FILD, FIMUL, FINCSTP, FINIT, FIST, FISTP, FISUB, FISUBR, FLD, FLD1, FLDCW, FLDENV, FLDENVW, FLDL2E, FLDL2T, FLDLG2, FLDLN2, FLDPI, FLDZ, FMUL, FMULP, FNCLEX, FNDISI, FNENI, FNINIT, FNOP, FNSAVE, FNSAVEW, FNSTCW, FNSTENV, FNSTENVW, FNSTSW, FPATAN, FPREM, FPTAN, FRNDINT, FRSTOR, FRSTORW, FSAVE, FSAVEW, FSCALE, FSQRT, FST, FSTCW, FSTENV, FSTENVW, FSTP, FSTSW, FSUB, FSUBP, FSUBR, FSUBRP, FTST, FWAIT, FXAM, FXCH, FXTRACT, FYL2X, FYL2XP1Added in specific processors
Added with 80287
FSETPM
Added with 80387
FCOS, FLDENVD, FNSAVED, FNSTENVD, FPREM1, FRSTORD, FSAVED, FSIN, FSINCOS, FSTENVD, FUCOM, FUCOMP, FUCOMPP
Added with Pentium Pro
- FCMOV variants: FCMOVB, FCMOVBE, FCMOVE, FCMOVNB, FCMOVNBE, FCMOVNE, FCMOVNU, FCMOVU
- FCOMI variants: FCOMI, FCOMIP, FUCOMI, FUCOMIP
Added with SSE
- FXRSTOR*, FXSAVE*
- Also supported on later Pentium IIs, though they do not contain SSE support
Added with SSE3
FISTTP (x87 to integer conversion)
Undocumented instructions
FFREEP performs FFREE ST(i) and pop stackSIMD instructions
MMX instructions
added with Pentium MMX EMMS, MOVD, MOVQ, PACKSSDW, PACKSSWB, PACKUSWB, PADDB, PADDD, PADDSB, PADDSW, PADDUSB, PADDUSW, PADDW, PAND, PANDN, PCMPEQB, PCMPEQD, PCMPEQW, PCMPGTB, PCMPGTD, PCMPGTW, PMADDWD, PMULHW, PMULLW, POR, PSLLD, PSLLQ, PSLLW, PSRAD, PSRAW, PSRLD, PSRLQ, PSRLW, PSUBB, PSUBD, PSUBSB, PSUBSW, PSUBUSB, PSUBUSW, PSUBW, PUNPCKHBW, PUNPCKHDQ, PUNPCKHWD, PUNPCKLBW, PUNPCKLDQ, PUNPCKLWD, PXORMMX+ instructions
added with Athlon
Same as the SSE SIMD Integer Instructions which operated on MMX registers.EMMX instructions
added with 6x86MX from Cyrix, deprecated now
PAVEB, PADDSIW, PMAGW, PDISTIB, PSUBSIW, PMVZB, PMULHRW, PMVNZB, PMVLZB, PMVGEZB, PMULHRIW, PMACHRIW3DNow! instructions
added with K6-2
FEMMS, PAVGUSB, PF2ID, PFACC, PFADD, PFCMPEQ, PFCMPGE, PFCMPGT, PFMAX, PFMIN, PFMUL, PFRCP, PFRCPIT1, PFRCPIT2, PFRSQIT1, PFRSQRT, PFSUB, PFSUBR, PI2FD, PMULHRW, PREFETCH, PREFETCHW3DNow!+ instructions
added with Athlon
PF2IW, PFNACC, PFPNACC, PI2FW, PSWAPDadded with Geode GX
PFRSQRTV, PFRCPVSSE instructions
added with Pentium III also see integer instruction added with Pentium IIISSE SIMD Floating-Point Instructions
ADDPS, ADDSS, CMPPS, CMPSS, COMISS, CVTPI2PS, CVTPS2PI, CVTSI2SS, CVTSS2SI, CVTTPS2PI, CVTTSS2SI, DIVPS, DIVSS, LDMXCSR, MAXPS, MAXSS, MINPS, MINSS, MOVAPS, MOVHLPS, MOVHPS, MOVLHPS, MOVLPS, MOVMSKPS, MOVNTPS, MOVSS, MOVUPS, MULPS, MULSS, RCPPS, RCPSS, RSQRTPS, RSQRTSS, SHUFPS, SQRTPS, SQRTSS, STMXCSR, SUBPS, SUBSS, UCOMISS, UNPCKHPS, UNPCKLPSSSE SIMD Integer Instructions
ANDNPS, ANDPS, ORPS, PAVGB, PAVGW, PEXTRW, PINSRW, PMAXSW, PMAXUB, PMINSW, PMINUB, PMOVMSKB, PMULHUW, PSADBW, PSHUFW, XORPS
SSE2 instructions
added with Pentium 4 also see integer instructions added with Pentium 4SSE2 SIMD Floating-Point Instructions
ADDPD, ADDSD, ANDNPD, ANDPD, CMPPD, CMPSD*, COMISD, CVTDQ2PD, CVTDQ2PS, CVTPD2DQ, CVTPD2PI, CVTPD2PS, CVTPI2PD, CVTPS2DQ, CVTPS2PD, CVTSD2SI, CVTSD2SS, CVTSI2SD, CVTSS2SD, CVTTPD2DQ, CVTTPD2PI, CVTPS2DQ, CVTTSD2SI, DIVPD, DIVSD, MAXPD, MAXSD, MINPD, MINSD, MOVAPD, MOVHPD, MOVLPD, MOVMSKPD, MOVSD*, MOVUPD, MULPD, MULSD, ORPD, SHUFPD, SQRTPD, SQRTSD, SUBPD, SUBSD, UCOMISD, UNPCKHPD, UNPCKLPD, XORPD
- CMPSD and MOVSD have the same name as the string instruction mnemonics CMPSD (CMPS) and MOVSD (MOVS), however, the former refer to scalar double-precision floating-points whereas the latters refer to doubleword strings.
SSE2 SIMD Integer Instructions
MOVDQ2Q, MOVDQA, MOVDQU, MOVQ2DQ, PADDQ, PSUBQ, PMULUDQ, PSHUFHW, PSHUFLW, PSHUFD, PSLLDQ, PSRLDQ, PUNPCKHQDQ, PUNPCKLQDQ
SSE3 instructions
added with Pentium 4 supporting SSE3 also see integer and floating-point instructions added with Pentium 4 SSE3SSE3 SIMD Floating-Point Instructions
- ADDSUBPD, ADDSUBPS (for Complex Arithmetic)
- HADDPD, HADDPS, HSUBPD, HSUBPS (for Graphics)
- MOVDDUP, MOVSHDUP, MOVSLDUP (for Complex Arithmetic)
SSSE3 instructions
added with Xeon 5100 series and initial Core 2- PSIGNW, PSIGND, PSIGNB
- PSHUFB
- PMULHRSW, PMADDUBSW
- PHSUBW, PHSUBSW, PHSUBD
- PHADDW, PHADDSW, PHADDD
- PALIGNR
- PABSW, PABSD, PABSB
SSE4 instructions
SSE4.1
added with Core 2 x9000 series
- MPSADBW
- PHMINPOSUW
- PMULLD, PMULDQ
- DPPS, DPPD
- BLENDPS, BLENDPD, BLENDVPS, BLENDVPD, PBLENDVB, PBLENDW
- PMINSB, PMAXSB, PMINUW, PMAXUW, PMINUD, PMAXUD, PMINSD, PMAXSD
- ROUNDPS, ROUNDSS, ROUNDPD, ROUNDSD
- INSERTPS, PINSRB, PINSRD/PINSRQ, EXTRACTPS, PEXTRB, PEXTRW, PEXTRD/PEXTRQ
- PMOVSXBW, PMOVZXBW, PMOVSXBD, PMOVZXBD, PMOVSXBQ, PMOVZXBQ, PMOVSXWD, PMOVZXWD, PMOVSXWQ, PMOVZXWQ, PMOVSXDQ, *PMOVZXDQ
- PTEST
- PCMPEQQ
- PACKUSDW
- MOVNTDQA
SSE4a
added with Phenom processors
- EXTRQ/INSERTQ
- MOVNTSD/MOVNTSS
SSE4.2
to be added with Nehalem processors
- CRC32
- PCMPESTRI
- PCMPESTRM
- PCMPISTRI
- PCMPISTRM
- PCMPGTQ
Undocumented instructions
The x86 CPUs contain undocumented instructions which are implemented on the chips but never listed in any official available document.| mnemonic | opcode | description | undoc status |
|---|---|---|---|
| AAM imm8 | D4 imm8 | Divide AL by imm8, put the quotient in AH, and the remainder in AL | Available beginning with 8086, documented since Pentium (earlier documentation lists no arguments) |
| AAD imm8 | D5 imm8 | Multiplication counterpart of AAM | Available beginning with 8086, documented since Pentium (earlier documentation lists no arguments) |
| SALC | D6 | Set AL depending on the value of the Carry Flag | Available beginning with 8086, but only documented since Pentium Pro. |
| ICEBP | F1 | Single byte single-step exception / Invoke ICE | Available beginning with 80386, documented (as INT1) since Pentium Pro |
| LOADALL | 0F 05 | Loads All Registers from Memory Address 0x000800H | Only available on 80286 |
| LOADALLD | 0F 07 | Loads All Registers from Memory Address ES:EDI | Only available on 80386 |
| POP CS | 0F | Pop top of the stack into CS Segment register | Only available on 8086. Beginning with 80286 this opcode is used as a prefix for 2-Byte-Instructions |
References
External links
- The 8086 / 80286 / 80386 / 80486 Instruction Set
- Free IA-32 and x86-64 documentation, provided by Intel
- Netwide Assembler x86 Instruction Reference (from Netwide Assembler)
- x86 Instruction Set Reference
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Last updated on Wednesday October 08, 2008 at 12:49:31 PDT (GMT -0700)
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This article is licensed under the GNU Free Documentation License.
Last updated on Wednesday October 08, 2008 at 12:49:31 PDT (GMT -0700)
View this article at Wikipedia.org - Edit this article at Wikipedia.org - Donate to the Wikimedia Foundation
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