Electrical limitations preclude connecting more than 2 unbuffered DDR SDRAM DIMMs or 4 buffered DIMMs to a single shared bus. It is also impractical to manufacture a single chip with more than two DDR memory buses (channels). Thus, it is impossible to connect more than 8 DIMMs to a single chip. This is typically the per-processor limitation as well.
The obvious solution is to use a narrower, higher-speed bus to interface to memory, and to implement it as a point-to-point link, daisy-chaining additional modules. However, Intel have made two attempts at this, neither hugely successful:
AMD's answer to this is the G3MX chip. This is very similar to the AMB, but is intended to be placed on the motherboard, not on the DIMM. It can connect to multiple DIMMs but, to minimize latency, is not designed to be daisy-chained.
The G3MX has an asymmetrical link to the processor, to match typical memory usage patterns. 20 differential signals supply read data to the processor, and 13 differential signals receive commands and write data. This totals 66 pins, less than half of what is required for a DDR2 or DDR3 interface. Thus, a processor can easily have 4 G3MX memory interfaces, each with 4 buffered DIMMs attached, allowing up to 16 DIMMs to feed one processor.