the encyclopedic entry of SSE4

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SSE4 subsets

Intel SSE4 consists of 54 instructions. A subset consisting of 47 instructions, referred to as SSE4.1 in some Intel documentation, is available in Penryn. Additionally, SSE4.2, a second subset consisting of the 7 remaining instructions, will first be available in Core i7 (formerly Nehalem). Intel, unusually, credits feedback from developers as playing an important role in the development of the instruction set.

AMD also added two new SSE instructions that it named SSE4a. These instructions are not found in Intel's processors supporting SSE4.1 and alternatively AMD processors are not supporting Intel's SSE4.1. Support was added for SSE4a for unaligned SSE load-operation instructions (which formerly required 16-byte alignment).

Name confusion

It should be noted that what is now known as SSSE3 (Supplemental Streaming SIMD Extension 3), introduced in the Intel Core 2 processor line, was mistakenly referred to as SSE4 by the media during its development.

New instructions

Unlike all previous iterations of SSE, SSE4 contains instructions that execute operations which are not specific to multimedia applications. It features a number of instructions whose action is determined by a constant field, and, in a rather surprising move, a set of instructions which take XMM0 as an implicit third operand. In addition, SSE4 totally lacks support for operations on 64-bit MMX registers; SIMD integer operations can be carried out on 128-bit XMM registers only.

Several of these instructions are enabled by the single-cycle shuffle engine in Penryn.

SSE4.1

Instruction	Description
MPSADBW	Compute eight offset sums of absolute differences (i.e. \|x₀-y₀\|+\|x₁-y₁\|+\|x₂-y₂\|+\|x₃-y₃\|, \|x₀-y₁\|+\|x₁-y₂\|+\|x₂-y₃\|+\|x₃-y₄\|, ...); this operation is extremely important for modern HDTV codecs, and (see ) allows an 8x8 block difference to be computed in fewer than seven cycles. One bit of a three-bit immediate operand indicates whether y₀ .. y₁₀ or y₄ .. y₁₄ should be used from the destination operand, the other two whether x₀..x₃, x₄..x₇, x₈..x₁₁ or x₁₂..x₁₅ should be used from the source.
PHMINPOSUW	Sets the bottom unsigned 16-bit word of the destination to the smallest unsigned 16-bit word in the source, and the next-from-bottom to the index of that word in the source.
PMULDQ	Packed signed multiplication on two sets of 2 out of 4 packed integers, the 1st and 3rd per packed 4, giving 2 packed 64-bit results.
PMULLD	Packed signed multiplication, 4 packed sets of 32-bit integers multiplied to give 4 packed 32-bit results.
DPPS, DPPD	Dot product for AOS (Array of Structs) data. This takes an immediate operand consisting of four (or two for DPPD) bits to select which of the entries in the input to multiply and accumulate, and another four (or two for DPPD) to select whether to put 0 or the dot-product in the appropriate field of the output.
BLENDPS, BLENDPD, BLENDVPS, BLENDVPD, PBLENDVB, PBLENDW	Conditional copying of elements in one location with another, based (for non-V form) on the bits in an immediate operand, and (for V form) on the bits in register XMM0.
PMINSB, PMAXSB, PMINUW, PMAXUW, PMINUD, PMAXUD, PMINSD, PMAXSD	Packed minimum/maximum for different integer operand types
ROUNDPS, ROUNDSS, ROUNDPD, ROUNDSD	Round values in a floating-point register to integers, using one of four rounding modes specified by an immediate operand
INSERTPS, PINSRB, PINSRD/PINSRQ, EXTRACTPS, PEXTRB, PEXTRW, PEXTRD/PEXTRQ	The INSERTPS and PINSR instructions read 8, 16 or 32 bits from an x86 register memory location and insert it into a field in the destination register given by an immediate operand, EXTRACTPS and PEXTR read a field from the source register and insert it into an x86 register or memory location. For example, PEXTRD eax, [xmm0], 1; EXTRACTPS [addr+4*eax], xmm1, 1 stores the first field of xmm1 in the address given by the first field of xmm0.
PMOVSXBW, PMOVZXBW, PMOVSXBD, PMOVZXBD, PMOVSXBQ, PMOVZXBQ, PMOVSXWD, PMOVZXWD, PMOVSXWQ, PMOVZXWQ, PMOVSXDQ, PMOVZXDQ	Packed sign/zero extension to wider types
PTEST	This does the same as the TEST instruction, in that it sets the ZF and CF flags to the result of an AND between its operators ... it sets the Z flag if any of the bits matched, and the C flag if all of them did.
PCMPEQQ	Quadword (64 bits) compare for equality
PACKUSDW	Convert signed DWORDs into unsigned WORDs with saturation.
MOVNTDQA	Efficient read from write-combining memory area into SSE register; this is useful for retrieving results from peripherals attached to the memory bus.

SSE4.2

Instruction	Description
CRC32	Accumulate CRC32C value using the polynomial 0x11EDC6F41 (or, without the high order bit, 0x1EDC6F41).
PCMPESTRI	Packed Compare Explicit Length Strings, Return Index
PCMPESTRM	Packed Compare Explicit Length Strings, Return Mask
PCMPISTRI	Packed Compare Implicit Length Strings, Return Index
PCMPISTRM	Packed Compare Implicit Length String, Return Mask
PCMPGTQ	Compare Packed Data For Greater Than
POPCNT	Population count (count number of bits set to 1) - bit manipulation; shares the same opcode for JMPE, the instruction used in Itanium CPUs to escape from IA-32 mode. POPCNT instruction may also be implemented in some processors that do not support the other SSE4 instructions and a separate bit can be tested to confirm POPCNT presence.

SSE4a

Instruction	Description
LZCNT	Leading Zero Count - bit manipulation. LZCNT instruction may also be implemented in some processors that do not support the other SSE4 instructions and a separate bit can be tested to confirm LZCNT presence.
POPCNT	Population count (count number of bits set to 1) - bit manipulation; shares the same opcode for JMPE, the instruction used in Itanium CPUs to escape from IA-32 mode. POPCNT instruction may also be implemented in some processors that do not support the other SSE4 instructions and a separate bit can be tested to confirm POPCNT presence.
EXTRQ/INSERTQ	Combined mask-shift instructions.
MOVNTSD/MOVNTSS	Scalar streaming store instructions.