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SPARC International, Inc

SPARC

SPARC (from Scalable Processor Architecture) is a RISC microprocessor instruction set architecture originally designed in 1985 by Sun Microsystems.

SPARC is a registered trademark of SPARC International, Inc., an organization established in 1989 to promote the SPARC architecture and to provide conformance testing. SPARC International was intended to open the SPARC architecture to make a larger ecosystem for the design, which has been licensed to several manufacturers, including Texas Instruments, Atmel, Cypress Semiconductor, and Fujitsu. As a result of SPARC International, the SPARC architecture is fully open and non-proprietary.

Implementations of the SPARC architecture were initially designed and used for Sun's Sun-4 workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68000 family of processors. Later, SPARC processors were used in SMP servers produced by Sun Microsystems, Solbourne and Fujitsu, among others.

Features

The SPARC architecture was heavily influenced by the earlier RISC designs including the RISC I & II from the University of California, Berkeley and the IBM 801. These original RISC designs were minimalist, including as few features or op-codes as possible and aiming to execute instructions at a rate of almost one instruction per clock cycle. This made them similar to the MIPS architecture in many ways, including the lack of instructions such as multiply or divide. Another feature of SPARC influenced by this early RISC movement is the branch delay slot.

The SPARC processor usually contains as many as 128 general purpose registers. At any point, only 32 of them are immediately visible to software - 8 are global registers (one of which, g0, is hard-wired to zero, so only 7 of them are usable as registers) and the other 24 are from the stack of registers. These 24 registers form what is called a register window, and at function call/return, this window is moved up and down the register stack. Each window has 8 local registers and shares 8 registers with each of the adjacent windows. The shared registers are used for passing function parameters and returning values, and the local registers are used for retaining local values across function calls. The "Scalable" in SPARC comes from the fact that the SPARC specification allows implementations to scale from embedded processors up through large server processors, all sharing the same core (nonprivileged) instruction set. One of the architectural parameters that can scale is the number of implemented register windows; the specification allows from 3 to 32 windows to be implemented, so the implementation can choose to implement all 32 to provide maximum call stack efficiency, or to implement only 3 to reduce context switching time, or to implement some number between them. Other architectures that include similar register file features include Intel i960, IA-64, and AMD 29000.

The architecture has gone through a few revisions. It gained hardware multiply and divide functionality in Version 8. The most substantial upgrade resulted in Version 9, which is a 64-bit (addressing and data) SPARC specification.

In SPARC Version 8, the floating point register file has 16 double precision registers. Each of them can be used as two single precision registers, providing a total of 32 single precision registers. An odd-even number pair of double precision registers can be used as a quad precision register, thus allowing 8 quad precision registers. SPARC Version 9 added 16 more double precision registers (which can also be accessed as 8 quad precision registers), but these additional registers can not be accessed as single precision registers.

Tagged add and subtract instructions perform adds and subtracts on values assuming that the bottom two bits do not participate in the computation. This can be useful in the implementation of the run time for ML, Lisp, and similar languages that might use a tagged integer format.

The 32-bit SPARC V8 architecture is purely big-endian. The 64-bit SPARC V9 architecture utilizes big-endian instructions, but can access data in either big-endian or little-endian byte order, chosen either at the application instruction (load/store) level or at the memory page level (via an MMU setting). The latter is often used for accessing data from inherently little-endian devices, such as those on PCI buses.

History

There have been three major revisions of the architecture. The first published revision was the 32-bit SPARC Version 7 (V7) in 1986. SPARC Version 8 (V8), an enhanced SPARC architecture definition, was released in 1990. SPARC V8 was standardized as IEEE 1754-1994, an IEEE standard for a 32-bit microprocessor architecture. SPARC Version 9, the 64-bit SPARC architecture, was released by SPARC International in 1993. In early 2006, Sun released an extended architecture specification, UltraSPARC Architecture 2005. UltraSPARC Architecture 2005 includes not only the nonprivileged and most of the privileged portions of SPARC V9, but also all the architectural extensions (such as CMT, hyperprivileged, VIS 1, and VIS 2) present in Sun's UltraSPARC processors starting with the UltraSPARC T1 implementation. UltraSPARC Architecture 2005 includes Sun's standard extensions and remains compliant with the full SPARC V9 Level 1 specification. The architecture has provided continuous application binary compatibility from the first SPARC V7 implementation in 1987 into the Sun UltraSPARC Architecture implementations.

As of December 2005 Sun announced their UltraSPARC T1 design would be open sourced, and in March 2006 the full source code became available via the OpenSPARC project.

Among various implementations of SPARC, Sun's SuperSPARC and UltraSPARC-I were very popular, and were used as reference systems for SPEC CPU95 and CPU2000 benchmarks. The 296 MHz UltraSPARC-II is the reference system for the SPEC CPU2006 benchmark.

SPARC64

Since 1995, Fujitsu (initially through its subsidiary, HAL Computer Systems) has designed SPARC V9-compliant processors under the SPARC64 brand, including the SPARC64 V, used in Fujitsu's PRIMEPOWER family of servers, and the SPARC64 VI, used by Sun and Fujitsu in their SPARC Enterprise M-class servers. As of mid-2008, the SPARC64 VII processor began shipping and is also used in M-class servers.

SPARC microprocessor specifications

I/O pins, dissipated power (watts), voltage, and cache sizes—data, instruction, L2 and L3 (kibibytes)."
Name
(Codename)
Model Frequency
[MHz]
Architecture
Version
Year Threads
Per Core × Cores
= Total Threads
Process
[µm]
Transistors
[millions]
Die size
[mm²]
IO Pins Power
[W]
Voltage
[V]
L1 Dcache
[k]
L1 Icache
[k]
L2 Cache
[k]
L3 Cache
[k]
SPARC (various) 14.28–40 V7 1987-1992 1×1=1 0.8–1.3 ~0.1–1.8 -- 160–256 -- -- 0–128 (unified) none none
microSPARC I (Tsunami) TI TMS390S10 40–50 V8 1992 1×1=1 0.8 0.8 225? 288 2.5 5 2 4 none none
SuperSPARC I (Viking) TI TMX390Z50 / Sun STP1020 33–60 V8 1992 1×1=1 0.8 3.1 -- 293 14.3 5 16 20 0-2048 none
SPARClite Fujitsu MB8683x 66–108 V8E 1992 1×1=1 -- -- -- 144–176 -- 2.5/3.3V 1–16 1–16 none none
hyperSPARC (Colorado 1) Ross RT620A 40–90 V8 1993 1×1=1 0.5 1.5 -- -- -- 5? 0 8 128-256 none
microSPARC II (Swift) Fujitsu MB86904 / Sun STP1012 60–125 V8 1994 1×1=1 0.5 2.3 233 321 5 3.3 8 16 none none
hyperSPARC (Colorado 2) Ross RT620B 90–125 V8 1994 1×1=1 0.4 1.5 -- -- -- 3.3 0 8 128-256 none
SuperSPARC II (Voyager) Sun STP1021 75–90 V8 1994 1×1=1 0.8 3.1 299 -- 16 -- 16 20 1024-2048 none
hyperSPARC (Colorado 3) Ross RT620C 125–166 V8 1995 1×1=1 0.35 1.5 -- -- -- 3.3 0 8 512-1024 none
TurboSPARC Fujitsu MB86907 160–180 V8 1995 1×1=1 0.35 3.0 132 416 7 3.5 16 16 512 none
UltraSPARC I (Spitfire) Sun STP1030 143–167 V9 1995 1×1=1 0.47 5.2 315 521 30 @167 MHz 3.3 16 16 512-1024 none
UltraSPARC I (Hornet) Sun STP1030 200 V9 1998 1×1=1 0.42 5.2 265 521 -- 3.3 16 16 512-1024 none
hyperSPARC (Colorado 4) Ross RT620D 180–200 V8 1996 1×1=1 0.35 1.7 -- -- -- 3.3 16 16 512 none
SPARC64 Fujitsu (HAL) 101–118 V9 1995 1×1=1 0.4 -- 297+163+142 286 50 3.8 128 128 -- --
SPARC64 II Fujitsu (HAL) 141–161 V9 1996 1×1=1 0.35 -- 202+103+84 286 64 3.3 128 128 -- --
SPARC64 III Fujitsu (HAL) MBCS70301 250–330 V9 1998 1×1=1 0.24 17.6 240 -- -- 2.5 64 64 8192 --
UltraSPARC IIs (Blackbird) Sun STP1031 250–400 V9 1997 1×1=1 0.35 5.4 149 521 25 @250 MHz 2.5 16 16 1024 or 4096 none
UltraSPARC IIs (Sapphire-Black) Sun STP1032 / STP1034 360–480 V9 1999 1×1=1 0.25 5.4 126 521 21 @400 MHz 1.9 16 16 1024–8192 none
UltraSPARC IIi (Sabre) Sun SME1040 270–360 V9 1997 1×1=1 0.35 5.4 156 587 21 1.9 16 16 256–2048 none
UltraSPARC IIi (Sapphire-Red) Sun SME1430 333–480 V9 1998 1×1=1 0.25 5.4 -- 587 21 @440 MHz 1.9 16 16 2048 none
UltraSPARC IIe (Hummingbird) Sun SME1701 400–500 V9 2000 1×1=1 0.18 Al -- -- 370 13 max @500 MHz 1.5-1.7 16 16 256 none
UltraSPARC IIi (IIe+) (Phantom) -- 550–650 V9 2002 1×1=1 0.18 Cu -- -- 370 17.6 1.7 16 16 512 none
SPARC64 GP Fujitsu SFCB81147 400–810 V9 2000 1×1=1 0.18 30.2 217 -- -- 1.8 128 128 8192 --
SPARC64 IV Fujitsu MBCS80523 450–810 V9 2000 1×1=1 0.13 -- -- -- -- -- 128 128 2048 --
UltraSPARC III (Cheetah) Sun SME1050 600 V9 2001 1×1=1 0.18 Al 29 330 1368 53 1.6 64 32 8192 none
UltraSPARC III (Cheetah) Sun SME1052 750–900 V9 2001 1×1=1 0.13 Al 29 -- 1368 -- 1.6 64 32 8192 none
UltraSPARC III Cu (Cheetah+) Sun SME1056 1002–1200 V9 2001 1×1=1 0.13 Cu 29 232 1368 80 @900 MHz 1.6 64 32 8192 none
UltraSPARC IIIi (Jalapeno) Sun SME1603 1064–1593 V9 2003 1×1=1 0.13 87.5 206 959 52 1.3 64 32 1024 none
SPARC64 V (Zeus) Fujitsu

1100–1350 V9/JPS1 2003 1×1=1 0.13 190 289 269 40 1.2 128 128 2048 --
SPARC64 V+ (Olympus-B) Fujitsu

1650–2160 V9/JPS1 2004 1×1=1 0.09 400 297 279 65 1 128 128 4096 --
UltraSPARC IV (Jaguar) Sun SME1167 1050–1350 V9 2004 1×2=2 0.13 66 356 1368 108 1.35 64 32 16384 none
UltraSPARC IV+ (Panther) Sun SME1167A 1500–2100 V9 2005 1×2=2 0.09 295 336 1368 90 1.1 64 64 2048 32768
UltraSPARC T1 (Niagara) Sun SME1905 1000–1400 V9 / UA 2005 2005 4×8=32 0.09 300 340 1933 72 1.3 8 16 3072 none
SPARC64 VI (Olympus-C) Fujitsu 2150–2400 V9/JPS2 2007 2×2=4 0.09 540 422 -- 120 -- 128 128 5120 none
UltraSPARC T2 (Niagara 2) Sun SME1908A 1000–1400 V9 / UA 2007 2007 8×8=64 0.065 503 342 1831 95 1.1–1.5 8 16 4096 none
UltraSPARC T2 Plus (Victoria Falls) Sun SME1910A 1200–1400 V9 / UA 2007 2008 8×8=64 0.065 503 342 1831 - - 8 16 4096 none
SPARC64 VII (Jupiter) Fujitsu 2400–2520 V9/JPS2(?) 2008 2×4=8 0.065 600 445 -- 135 -- 64 64 6144 none
UltraSPARC RK (Rock) Sun SME1832 2300 V9 / UA__?__ 2009 2×16=32 0.065 ? 396 2326 ? ? 32 32 + 8 predecoded bits 2048 ?
Name Model Frequency
[MHz]
Architecture
Version
Year Threads
Per Core × Cores
= Total Threads
Process
[µm]
Transistors
[millions]
Die size
[mm²]
IO Pins Power
[W]
Voltage
[V]
L1 Dcache
[k]
L1 Icache
[k]
L2 Cache
[k]
L3 Cache
[k]

Operating system support

SPARC machines have generally used Sun's SunOS or Solaris Operating Systems, but other operating systems such as NEXTSTEP, RTEMS, FreeBSD, OpenBSD, NetBSD, and Linux are also used on SPARC-based systems.

In 1993, Intergraph announced a port of Windows NT to the SPARC architecture, but it was later canceled.

Open source implementations

Three fully open source implementations of the SPARC architecture exist.

  • LEON, a 32-bit, single-thread SPARC Version 8 implementation, designed especially for outer space uses. Source code is written in VHDL, and licensed under the GPL.
  • OpenSPARC T1, released in 2006, a 64-bit, 32-thread implementation conforming to the UltraSPARC Architecture 2005 and to SPARC Version 9 (Level 1). Source code is written in Verilog, and licensed under many licenses. Most OpenSPARC T1 source code is licensed under the GPL. Source based on existent open source projects will continue to be licensed under their current licenses. Binary programs are licensed under a binary Software License Agreement.
    • S1, a 64-bit Wishbone compliant CPU core based on the OpenSPARC T1 design. It is a single UltraSPARC v9 core capable of 4 way SMT. Like the T1, the source code is licensed under the GPL.
  • OpenSPARC T2, released in 2008, a 64-bit, 64-thread implementation conforming to the UltraSPARC Architecture 2007 and to SPARC Version 9 (Level 1). Source code is written in Verilog, and licensed under many licenses. Most OpenSPARC T2 source code is licensed under the GPL. Source based on existent open source projects will continue to be licensed under their current licenses. Binary programs are licensed under a binary Software License Agreement.

Supercomputers

As of November 2007, only one of the world's top 500 fastest supercomputers is based on SPARC64 processors:

This list compares unfavorably with other processor architectures, which make up a much larger portion of the top 500 list. The SPARC processor family had 88 of the top 500 systems in June 2002, but has since lost popularity to faster chips from IBM, Intel, and AMD.

References

See also

External links

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