Each entry contains the following information for each interrupt signal line:

• Whether the line is masked (enabled)
• Whether the line should be edge or level triggered
• Signal polarity for level interrupts: active when low or active when high
• Which CPU(s) the interrupt should be routed to
• How the target CPU(s) should deliver the interrupt to software, including
• Which legacy interrupt vector the target CPU(s) should route the interrupt to (effectively controls priority)

See also

• Intel APIC Architecture

External links

• Datasheet for Intel 82093AA IOAPIC