The POWER6 microprocessor is IBM's follow-on to the POWER5. It is part of the eCLipz project, said to have a goal of converging IBM's server hardware where practical (hence "ipz" in the acronym: iSeries, pSeries, and zSeries). POWER6 was described at the IEEE International Solid-State Circuits Conference (ISSCC) in February 2006, and additional details were added at the Microprocessor Forum in October 2006 and at the next ISSCC in February 2007. It was formally announced on 21 May 2007 As of October 2008, POWER6 is the fastest microprocessor in the industry at per-core basics.


The POWER6 has approximately 790 million transistors and is 341 mm² large fabricated on a 65 nm process. It was released on the 8th June 2007, at speeds of 3.5 GHz, 4.2 GHz and 4.7 GHz, but the company has noted prototypes have reached 6 GHz. POWER6 reached first silicon in the middle of 2005, and bumped to 5.0 GHz in October 2008. Dr Frank Soltis, an IBM chief scientist, said IBM had solved power leakage problems associated with high frequency by using a combination of 90 nm and 65 nm parts in the POWER6 design.

The processor is a dual core design and has 128 KiB of L1 cache (64 KiB data + 64 KiB instruction), an eight-way set-associative design with a two-stage pipeline supporting two independent 32-bit reads or one 64-bit write per cycle. Each core will have a 4 MiB "semi shared" L2 cache, where the cache is assigned a specific core, but the other has a fast access to it. The two cores share a 32 MiB large L3 cache which is off die, using an 80 GB/s bus. Each core has two integer units, two binary floating-point units, and a novel decimal floating-point unit, and is capable of two way SMT. The binary floating-point unit incorporates “many microarchitectures, logic, circuit, latch and integration techniques to achieve [a] 6-cycle, 13-FO4 pipeline,” according to a company paper. Unlike the servers from IBM's competitors, the POWER6 has hardware support for IEEE 754 decimal arithmetic and includes the first decimal floating-point unit integrated in silicon. More than 50 new floating point instructions handle the decimal math and conversions between binary and decimal. This is a feature also added to the processors powering IBM's System z. There is an AltiVec unit to POWER6, and the processor is fully compliant with the new Power ISA v.2.03 specification. POWER6 also takes advantage of ViVA-2, Virtual Vector Architecture, which enables the combination of several POWER6 nodes to act as a single Vector processor.

A notable difference from POWER5 is that IBM moved from an out-of-order design to an in-order design, a change which often requires software recompilation for optimized performance. However, the processor still achieves significant performance improvements even with unmodified software, according to the lead engineer on the POWER6 project.

IBM also makes use of a 5 GHz duty-cycle correction clock distribution network for the processor. In the network, the company implements a copper distribution wire that is 3 µm wide and 1.2 µm thick. The POWER6 design uses dual power supplies, a logic supply in the 0.8-to-1.2 Volt range and an SRAM power supply at about 150-mV higher.. The thermal characteristics of POWER6 are similar to that of the POWER5.

POWER6 can connect to up to 31 other processors using two inter node links (50 GB/s), and supports up to 1024 virtual partitions. POWER6 comes in MCMs just like POWER5 with up to four processor dies and associated external L3 cache on a single substrate. There is an interface to a service processor that monitors and adjusts performance and power according to set parameters.


IBM Power Systems run on the Power 6 CPU. The systems are the 520 Express, 550 Express, Power 570, Power 575, and Power 595. Power systems running AIX vs i have different model designations but the hardware is essentially identical. Power Systems. The various system models are designed to serve any sized business. For example, the 520 Express is marketed to small businesses while the Power 595 is basically a mainframe. All Power systems are noted for their huge expansion and storage capabilities.

IBM also offers two Power 6 based single wide blade servers, the JS12 and the JS22. blade module. The JS12 is equipped with (2) 3.8GHz Power 6 cores while the JS22 has (4) 4.0GHz Power 6 cores. Both blades support AIX, i, and Linux. The BladCenter S and H chassis is supported for blades running AIX, i, and Linux. The BladeCenter E, HT, and T chassis support blades running AIX and Linux but not i.

At the SuperComputing 2007 (SC07) conference in Reno a new water-cooled p575 was also revealed with 32 POWER6 cores at 4.7 GHz with up to 256 GB of RAM.


POWER6 includes redundancy-circuitry, support for mainframe instructions, and many power saving features, so there are plans to make stripped down, low power versions for applications like blade systems, and single core versions. The POWER6L is a low end derivative of POWER6 in the same segment as PowerPC 970 and there have been rumors of an ultra-light version, POWER6UL. IBM is also investigating a high-end four core version manufactured on a 45 nm process.

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