Oscillation hazard

Hazard (logic)

Logic circuits use boolean gates to perform some function as a result of some inputs. An ideal gate has an instantaneous change in state when its inputs change, but in reality there is actually some delay.

A hazard or glitch in digital logic is a fault in the logic system due to a change at the input. A static hazard is when the output of a logic circuit momentarily changes when its final value is the same as its value before the hazard (when the output is "trying" to remain the same, it jumps once, then settles down). For example, output going from 0 to 1 to 0 (it's "trying" to stay at zero but failing once - thus the hazard). A dynamic hazard (or oscillation hazard) is where a logic circuit will momentarily change back to its original value while changing to a new value. For example, output going from 0 to 1 to 0 and finally to 1 (it's "trying" to go from simply 0 to 1).

The cause of hazards is the timing delay of different components in the circuit. When certain paths through the circuit allow a variable-change to propagate faster than other paths, this may cause glitches.

The resulting glitches in the circuit may or may not induce additional problems - other than increased issues due to switching noise. It is good design practice to design circuits to minimize these hazards.

There are two types of static hazards: a low-going glitch (or static one hazard) is where the high output transitions to a low and back high (1-0-1) and a high-going glitch (or static zero hazard) is where the low output transitions to a high and back low (0-1-0).

Static 0 hazards occur in product-of-sums implementations, but do not occur in sum-of-products implementations. Static 1 hazards occur in sum-of-products implementations, but do not occur in product-of-sums implementations.


A Karnaugh map is the easiest way to eliminate static hazards. These timing hazards will develop as random or intermittent circuit failures. The type of circuit failure will depend on the signals used in the circuit, and perhaps how often they change state.

Another method to eliminate timing hazards from affecting an integrated circuit down the line is to re-clock the final output signals. Re-clocking the signal does not eliminate the glitch, but stops it from causing circuit failure. Re-clocking the signal seems to be common for designers unsure of why the glitch occurs, or how to stop the glitch from developing. Solving the problem via a Karnaugh map usually results in more devices (a non-minimal circuit), while re-clocking requires an additional flip-flop.

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