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INPUT A B | OUTPUT A NOR B | |

0 | 0 | 1 |

0 | 1 | 0 |

1 | 0 | 0 |

1 | 1 | 0 |

The NOR gate is a digital logic gate that implements logical NOR - it behaves according to the truth table to the right. A HIGH output (1) results if both the inputs to the gate are LOW (0). If one or both input is HIGH (1), a LOW output (0) results. NOR is the result of the negation of the OR operator. NOR is a functionally complete operation -- combinations of NOR gates can be combined to generate any other logical function. By contrast, the OR operator is monotonic as it can only change LOW to HIGH but not vice versa.

In most, but not all, circuit implementations, the negation comes for free -- including CMOS and TTL. In such logic families, the only way to implement OR is with 2 or more gates, such as a NOR followed by an inverter. A significant exception is some forms of the domino logic family.

There are two symbols for NOR gates: the American ('military') symbol and the IEC ('European' or 'rectangular') symbol. For more information see Logic Gate Symbols.

NOR Gates are basic logic gates, and as such they are recognised in TTL and CMOS ICs. The standard, 4000 series, CMOS IC is the 4001, which includes four independent, two-input, NOR gates. The pinout diagram is as follows:

1 Input A1 2 Input B1 3 Output Q1 4 Output Q2 5 Input B2 6 Input A2 7 V 8 Input A3 9 Input B3 10 Output Q3 11 Output Q4 12 Input B4 13 Input A4 14 V |

The standard 2-, 3-, 4- and 8-input NOR gates are available:

- CMOS
- 4001: Quad 2-input NOR gate
- 4025: Triple 3-input NOR gate
- 4002: Dual 4-input NOR gate
- 4078: Mono 8-input NOR gate
- TTL
- 7402: Quad 2-input NOR gate
- 7427: Triple 3-input NOR gate
- 7425: Dual 4-input NOR gate
- Mono 8-input NOR gate is not available in TTL

This diagram shows the construction of a 2-input NOR gate using NMOS circuitry. If either of the inputs are high, the corresponding NMOS is turned on and the output is pulled low; otherwise the output is pulled high through the pull-up resistor.

If no specific NOR gates are available, one can be made from NAND gates in the configuration shown below. Interestingly, any logic gate can be made either from a combination of NAND gates or from a combination of NOR gates.

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Last updated on Tuesday September 23, 2008 at 01:18:40 PDT (GMT -0700)

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This article is licensed under the GNU Free Documentation License.

Last updated on Tuesday September 23, 2008 at 01:18:40 PDT (GMT -0700)

View this article at Wikipedia.org - Edit this article at Wikipedia.org - Donate to the Wikimedia Foundation

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