While Kalb was the Vice-President of DEC's VLSI chip-building division, some researchers in that division were building a supercomputer based on the Goodyear MPP (massively parallel processor) supercomputer. The DEC researchers enhanced the architecture by:
After Digital decided not to productize the research project, Kalb decided to start a company to sell this minisupercomputer. In 1990, the first generation product MP-1 was delivered. In 1992, the follow-on MP-2 was shipped. The company shipped a total of 200 systems. Samples of MasPar MPs, from the NASA Goddard Space Flight Center, are in storage at the Computer History Museum.
Maspar offered a family of SIMD machines, second sourced by DEC. The processor units are proprietary.
MasPar exited the hardware business in June 1996. The new software company was called NeoVista. There were over 250 MP-2 installations. There was no MP-3.
MasPar is unique in being a manufacturer of SIMD supercomputers (as opposed to vector machines). In this approach, a collection of ALU's listen to a program broadcast from a central source. The ALUs can do their own data fetch, but are all under control of a central Array Control Unit. There is a central clock. The emphasis is on communications efficiency, and low latency. The MasPar architecture is designed to scale, and balance processing, memory, and communication.
The Array Control Unit (ACU) handles instruction fetch. It is a load-store architecture. The MasPar architecture is Harvard in a broad sense. The ACU implements a microcoded instruction fetch, but achieves a RISC-like 1 instruction per clock. The Arithmetic units, ALU's with data fetch capability, are implemented 32 to a chip. Each ALU is connected in a nearest neighbor fashion to 8 others. The edge connections are brought off-chip. In this scheme, the perimeters can be toroid-wrapped. Up to 16,384 units can be connected within the confines of a cabinet. A global router, essentially a cross-bar switch, provides external I/O to the processor array.
The MP-2 PE chip contains 32 processor elements, each a full 32-bit ALU with floating point, registers, and a barrel shifter. Only the instruction fetch feature is removed, and placed in the ACU. The PE design is literally replicated 32 times on the chip. The chip is designed to interface to DRAM, to other processor array chips, and to communication router chips.
Each ALU, called a PE slice, contains sixty four 32 bit registers that are used for both integer and floating point. The registers are, interestingly, bit and byte addressable. The floating point unit handles single precision and double precision arithmetic on IEEE format numbers. Each PE slice contains two registers for data memory address, and the data. Each PE also has two one-bit serial ports, one for inbound and one for outbound communication to its nearest neighbor. The direction of communication is controlled globally. The PEs also have inbound and outbound paths to a global router for I/O. A broadcast port allows a single instance of data to be "promoted" to parallel data. Alternately, global data can be 'or-ed' to a scalar result.
The serial links support 1 Mbyte/s bit-serial communication that allows coordinated register-register communication between processors. Each processor has its own local memory, implemented in DRAM. No internal memory is included on the processors. Microcoded instruction decode is used.
The 32 PEs on a chip are clustered into two groups sharing a common memory interface, or M-machine, for access. A global scoreboard keeps track of memory and register usage. The path to memory is 16 bits wide. Both big and little endian formats are supported. Each processor has its own 64 Kbyte of memory. Both direct and indirect data memory addressing are supported.
There is no cache for the ALU's. Cache is not required, due to the memory interface operating at commensurate speed with the alu data accesses.
Raytheon picks MasPar processors for GBR sensor. (MasPar Computer Corp.'s MP-2 massively parallel processing system chosen for Theater Missile Defense Ground Based Radar system)
Dec 14, 1993; Maspar Computer Corp.'s MP-2 massively parallel processing (MPP) system has been selected by Raytheon Co. for the Theater...
MasPar given $20 million contract for new computer technology. (Advanced Research Projects Agency contract for massively parallel processing)
Jun 18, 1993; The Pentagon's Advanced Research Projects Agency DoD awarded a $20 million, two-year research contract to Maspar Computer...
SofTech Inc. of Waltham, Mass., and massively-parallel supercomputer maker MasPar Computer Corp. have reached an agreement for SofTech to provide consultative and systems integration services to existing and future MasPar customers. (Mergers/ Acquisitions/ Alliances)
Feb 01, 1993; SofTech Inc. of Waltham, Mass., and massively-parallel supercomputer maker Maspar Computer Corp. have reached an agreement...
DEC to be software integrator for massively parallel computer market. (joint venture with Maspar Computer Corp.) (Digital Equipment Corp.)
Apr 15, 1991; DEC TO BE SOFTWARE INTEGRATOR FOR MASSIVELY PARALLEL COMPUTER MARKET In one week or so, Digital Equipment Corp. is expected to...