Instruction Set Architecture

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Complex instruction set computer

A complex instruction set computer (CISC, pronounced like "sisk") is a microprocessor instruction set architecture (ISA) in which each instruction can execute several low-level operations, such as a load from memory, an arithmetic operation, and a memory store, all in a single instruction. The term was retroactively coined in contrast to reduced instruction set computer (RISC).

Historical design context

Incitements and benefits

Before the RISC philosophy became prominent, many computer architects tried to bridge the so called semantic gap, i.e. to design instruction sets that directly supported high-level programming constructs such as procedure calls, loop control, and complex addressing modes, allowing data structure and array accesses to be combined into single instructions. The compact nature of such instruction sets results in smaller program sizes and fewer calls to main memory, which at the time (early 1960s and onwards) resulted in a tremendous savings on the cost of computer memory and disc storage. It also meant good programming productivity even in assembly language, as high level languages such as Fortran or Algol were not always available or appropriate.

Problems

While many designs achieved the aim of higher throughput at lower cost and also allowed high-level language constructs to be expressed by fewer instructions, it was observed that this was not always the case. For instance, low-end versions of complex architectures (i.e. using less hardware) could lead to situations where it was possible to improve performance by not using a complex instruction (such as a procedure call or enter instruction), but instead using a sequence of simpler instructions.

One reason for this was that architects (microcode writers) sometimes "over-designed" assembler language instructions, i.e. including features which were not possible to implement efficiently on the basic hardware available. This could, for instance, be "side effects" (above conventional flags), such as the setting of a register or memory location that were perhaps seldom used; if this were done via ordinary (non duplicated) internal buses (or even the external bus), it would demand extra cycles every time, and thus be quite inefficient.

Even in balanced high performance designs, such (relatively) high level instructions which are typically also highly encoded (for good code density), could be complicated to decode and execute efficiently within a limited transistor budget. These architectures therefore require a great deal of work on the part of the processor designer in cases where a simpler, but (normally) slower, solution based on decode tables and/or microcode sequencing is not appropriate. At the time where transistors were a limited resource, this also left less room on the processor to optimize performance in other ways, which gave room for ideas to return to simpler processor-designs in order to make it more feasible to cope without ROMs (or even PLAs) for sequencing or decoding. This led to the first RISC-labeled processors in the mid-1970s (IBM 801 - IBMs Watson Research Center).

Transistors for logic, PLAs, and microcode are no longer a scarce resource however (only for huge caches, basically), and together with better tools and new technologies, this has led to new implementations of highly encoded and variable length designs without load-store limitations (i.e. non RISC). This governs both re-implementations of older instruction-sets (such as the ubiquitous x86, see below), as well as new designs for microcontrollers for embedded systems, and similar uses.

CISC and RISC processors

Examples of CISC processors are the System/360 (excluding the 'scientific' Model 44), VAX, PDP-11, Motorola 68000 family, and Intel x86 architecture based processors.

The terms RISC and CISC have become less meaningful with the continued evolution of both CISC and RISC designs and implementations. The first highly pipelined "CISC" implementations, such as 486s from Intel, AMD, Cyrix, and IBM, certainly supported every instruction that their predecessors did, but achieved high efficiency only on a fairly simple x86 subset (resembling a RISC instruction set, but without the load-store limitations of RISC). Modern x86 processors also decode and split more complex instructions into a series of smaller internal "micro-operations" which can thereby be executed in a pipelined (parallel) fashion, thus achieving high performance on a much larger subset of instructions.