The largest fraction of silicon integrated circuit respins are due, at least in part, to functional errors. Thus, comprehensive functional verification is key to reducing development costs and delivering a product on time. Functional verification of a design is most often performed using logic simulation and/or prototyping. There are advantages and disadvantages to each and often both are used. Logic simulation is easy, accurate, flexible, and low cost. However, simulation is often not fast enough for large designs and almost always too slow to run application software against the hardware design. FPGA-based prototypes are fast and inexpensive. But the time required to implement a large design into several FPGAs can be very long and is error-prone. Changes to fix design flaws also take a long time to implement and may require board wiring changes. Since FPGA prototypes have little debugging capability, probing signals inside the FPGAs in real time is very difficult, if not impossible, and recompiling FPGAs to move probes takes too long. The usual compromise is to use simulation early in the verification process when bugs and fixes are frequent, and prototyping at the end of the development cycle when the design is basically complete and speed is needed to get sufficient testing to uncover any remaining system-level bugs. Prototyping is also popular for testing software.
Simulation acceleration can address the performance shortcomings of simulation to an extent. Here the design is mapped into a hardware accelerator to run much faster and the testbench (and any behavioral design code) continues to run on the simulator on the workstation. A high-bandwidth, low latency channel connects the workstation to the accelerator to exchange signal data between testbench and design. By Amdahl's law, the slowest device in the chain will determine the speed achievable. Normally, this is the testbench in the simulator. With a very efficient testbench (written in C or transaction-based), the channel may become the bottleneck. In some cases, a transaction-level testbench is able to feed as much data to the design being emulated as "live" stimulus.
In-circuit emulation improves greatly on FPGA prototyping’s long time to implement and change designs, and provides a comprehensive, efficient debugging capability. While it takes weeks or months to implement an FPGA prototype, it takes only days to implement emulation. And design changes take but a few hours or less. Emulation does this at the expense of running speed and cost compared to FPGA prototypes. Looking at emulation from the other direction, it improves on acceleration’s performance by substituting "live" stimulus for the simulated testbench. This stimulus can come from a target system (the product being developed), or from test equipment. At 10,000 to 100,000 times the speed of simulation, emulation is often the only technique that can deliver the speed necessary to test application software while still providing a comprehensive hardware debug environment.
It is worth noting that simulation and prototyping involve two different styles of execution. Simulation executes the RTL code serially while a prototype executes fully in parallel. This leads to differences in debugging. In simulation:
With a prototype:
Acceleration and emulation are more like prototyping and silicon in terms of RTL execution and debugging since the entire design executes simultaneously as it will in the silicon. Since the same hardware is often used to provide both simulation acceleration and in-circuit emulation, these systems provide a blend of these two very different debugging styles.
High end hardware emulators provide a debugging environment with many features that can be found in logic simulators, and in some cases even surpass their debugging capabilities:
Another difference between simulation and acceleration and emulation is a consequence of accelerators using hardware for implementation – they have only two logic states – acting the way the silicon will when fabricated. This implies:
A key distinction between an emulator and an FPGA prototyping system is that the emulator provides a rich debug environment while a prototyping system has little to no debug capability and is primarily used after the design is debugged to create multiple copies for system analysis and software development.
Patent No. 7,739,097 Issued on June 15, Assigned to Quickturn Design Systems for Hardware Emulation System (California, Oregon Inventors)
Jun 16, 2010; ALEXANDRIA, Va., June 22 -- Mikhail Bershteyn of Campbell, Calif., Jerry R. Bauer of Cupertino, Calif., Stephen P. Sample of...
US Patent Issued to Cadence Design Systems on Sept. 27 for "Method and Apparatus for Synchronizing Processors in a Hardware Emulation System" (California, New York Inventors)
Oct 03, 2011; ALEXANDRIA, Va., Oct. 3 -- United States Patent no. 8,027,828, issued on Sept. 27, was assigned to Cadence Design Systems Inc....