The charter for the development and production of the DEC 2000 AXP was held by Digital's Entry Level Solutions Business, based in Ayr, Scotland. Workstation variants of these systems were later succeeded by the entry-level Multia and the entry-level and mid-range models of the AlphaStation family, while sever variants were succeeded by entry-level models of the AlphaServer family.
There are three models in the DEC 2000 AXP family:
The DECpc AXP 150 running Windows NT was intended to be used as a workstation and therefore can only use a VGA monitor. The Model 300 and 500, intended to be used as servers running OpenVMS or DEC OSF/1 AXP can only use a VT-series terminal or equivalent.
The DEC 2000 AXP has a 128-bit memory subsystem and supports 16 to 128 MB of memory. Standard 36-bit, 70 nanosecond SIMMs with longword parity protection are used to populate eight SIMM slots, which are organised in two banks of four slots each. The DEC 2000 AXP supports two memory options, a 16 MB (4 × 4 MB SIMMs) and a 64 MB (4 × 16 MB SIMMs) memory kit.
The DEC 2000 AXP provides six EISA slots for expansion. Pre-installed EISA cards typically comprised a Compaq QVision VGA adapter, Adaptec AHA-1742 SCSI host adapter, and a DEC DE422 Ethernet adapter.
Unlike other similar Alpha systems from Digital at the time, such as the DEC 3000 AXP, the DEC 2000 AXP used the EISA bus for expansion instead of the TURBOchannel interconnect. The decision to use the EISA bus was due to cost requirements. The EISA bus was an industry standard bus, and there were more vendors offering EISA options, in addition to EISA chipsets. In contrast, the TURBOchannel bus, while offering higher performance, would have required more expensive ASICs to implement like the DEC 3000 AXP, and would have reduced the number of third-party options available.
Because the DECchip 21064's signalling is incompatible with the EISA chipset and the system peripherals, the DECchip signals are interfaced to two buses, an address and command bus and a 32-bit data bus that masquerades as the 80486 interfaces. These two buses are referred to as "pseudo-486". The EISA bus itself was implemented by a subset of the Intel 82350DT chipset. The 82358 EBC (EISA Bus Controller) chip and 82357 ISP (Integrated System Peripheral) chip implements the EISA bus and provides it with an interface to the system. Two 82352 EBB (EISA Bus Buffer) chips are also present, with one used to interface the EISA bus to a 32-bit pseudo-486 data bus, and the other used to interface the EISA bus to a pseudo-486 address and command bus.
This arrangement of buffering and converting buses and control signals resulted in an inefficient I/O subsystem and as a result, the EISA bus only achieved a peak bandwidth of 25 MB/s (compared to 33 MB/s in standard PCs).
A VLSI Technologies VL82C106 combination chip, connected to the pseudo-486 buses, contains the real time clock and 66 bytes of battery-backed RAM, in addition to two serial line interfaces, a LPT interface and two PS/2 port interfaces. The real time clock and the battery-backed RAM draws power from an external 4.5 volt battery pack. The battery-backed RAM was primarily used to store system configuration information.