DEC 7000

DEC 7000/10000 AXP

The DEC 7000 AXP and DEC 10000 AXP are a series of high-end multiprocessor server computers developed and manufactured by Digital Equipment Corporation, introduced on 10 November, 1992 (although the DEC 10000 AXP was not available until the following year). These systems formed part of the first generation of systems based on the 64-bit Alpha AXP architecture and at the time of introduction, ran Digital's OpenVMS AXP or OSF/1 AXP operating systems. They were designed in parallel with the VAX 7000 and 10000 minicomputers, and are identical except for the processor module(s) and supported bus interfaces. A field upgrade from a VAX 7000/10000 to a DEC 7000/10000 AXP was possible by means of swapping the processor boards.

The DEC 7000/10000 AXP were intended to supersede the VAX 6000 series, and themselves were succeeded in 1995 by the AlphaServer 8200 (TurboLaser) enterprise server.

Models

The DEC 10000 AXP was essentially a larger configuration of the DEC 7000 AXP. Both shared the same System Cabinet, but the 10000 was configured as standard with one Expander Cabinet housing storage devices, and one Battery Cabinet housing a uninterruptible power supply. These were optional for a DEC 7000 AXP system.

There are two models of the DEC 7000 AXP:

Model 6x0, code named Laser/Ruby: 182 MHz DECchip 21064 (EV4) processor(s), later available with 200 MHz 21064s (Laser/Ruby+). It was discontinued on June 10, 1995 and on December 31, 1995 for Europe. Upgrades were offered for an addition year after discontinuation.
Model 7x0, code named Laser/Ruby45: 275 MHz DECchip 21064A (EV45) processor(s). This model was introduced on November 3, 1994.

There was one model of the DEC 10000 AXP:

Model 6x0, code named Blazer/Ruby: 200 MHz DECchip 21064 (EV4) processor(s).

The possible values of 'x' is 1 to 6. These numbers specify the number of microprocessors in the system.

Hardware description

The DEC 7000/10000 AXP are six-way SMP capable systems based on nine nodes that are interconnected by the 128-bit LSB (Laser System Bus) bus. The bus, which is pipelined, runs at 50 MHz and yields a maximum usable bandwidth of 640 MB/s. Eight of the nine nodes can be populated by a combination of CPU and memory modules, as long as the number of CPU modules is one to six, and one to seven for memory modules. The inclusion of a I/O module at node nine is mandatory and the slot for the module was physically incompatible with other modules to ensure this.

The nodes are printed circuit boards that plug into slots on a centerplane, which contains the LSB bus. The nodes and centerplane are housed in the LSB card cage, located on the top right quadrant of the cabinet. The front side of centerplane, from left to right, has four slots for nodes zero to three and a Power Filter module while the rear side, from left to right, has five slots for nodes four to eight. Slot eight is reserved for the I/O module.

CPU module

Numerous CPU modules were available for these systems. The initial VAX 7000/10000 Model 600 used the KA7AA module, which featured a 90.9 MHz NVAX+ microprocessor, while later VAX-based systems such as the Model 700 and 800 used the KA7AB and KA7AC modules, which featured faster NVAX5 microprocessors. The Alpha-based DEC 7000/10000 Model 600 AXP used the KN7AA module which featured a 182 MHz DECchip 21064 microprocessor initially, which was later upgraded to 200 MHz. The Model 700 used the KN7AB module featuring 275 MHz DECchip 21064A. Other than the differences in microprocessor and clock frequencies, all CPU modules also featured 4 MB of Bcache (L2 cache) and two LEVI gate arrays for interfacing the module to the LSB bus. The CPU modules are interchangeable and Digital intended customers with the VAX-based systems to eventually upgrade to the Alpha by simply swapping them.

Memory module

The DEC 7000/10000 uses the MS7AA memory module with capacities of 64 MB, 128 MB, 256 MB, 512 MB, 1 GB and 2 GB. The module and its components are clocked at 50 MHz. The MIC (Memory Interface Controller), provides the interface to the LSB bus, and is comprised of two gate arrays, MIC-A and MIC-B. The two gate arrays both provide a 64-bit data path, which when combined results in a 128-bit data path that matches the width of the LSB bus. The two gate arrays, while similar, are not identical. MIC-A also serves as the memory controller, interfaces to the LSB bus' control lines and coordinates the operation of MIC-B, which provides the module with SECDED ECC capability.

Also on the module are 18 MDC (Memory Data Controller) chips. The purpose of the MDCs is to act as a buffer between the 512-bit memory bus and the 128-bit LSB bus. During memory read operations, the MDCs buffer a 512-bit transaction from the memory and forwards it to the MIC in four 128-bit transactions over four 20 nanosecond cycles. Memory write operations are similar, but with the roles reversed. The MDCs instead accumulate four 128-bit transactions from the MIC over four 20 nanosecond cycles before writing to the memory in one 512-bit transaction.

The memory is implemented with 4 or 16 MB DRAM chips and organised into one to eight 'strings', each consisting of 144 DRAM chips. Depending on the module's capacity, the DRAM chips are either surface mounted on both sides of the board or mounted on SIMMs that are soldered onto the board. The SIMMs are not socketed as Digital's engineers found the arrangement to be unreliable.

The modules and the memory subsystem of the DEC 7000/1000 supports interleaving. Modules with more than two strings supports two-way interleaving. At a system level, the memory subsystem supports a maximum of eight-way interleaving. If the configuration results in more levels of interleaving than the memory subsystem can support, multiple memory modules are then grouped into larger banks so the level of interleaving in the memory subsystem does not exceed the maximum of eight ways.

I/O module

The I/O module contains four parallel ports (not to be confused with the parallel ports found in personal computers) that connect to expansion drawers or cabinets via three meter long cables. The expansion drawers or cabinets then implement different buses such the FutureBus+ Profile B and XMI expansion buses and the SCSI and DSSI (Digital's implementation of SCSI with proprietary extensions) disk drive interfaces. Also on the I/O module is a I/O controller gate array, whose purpose is to interface the module to the LSB bus and to serve as a bridge, receiving a transaction from a bus and passing it on to another. The I/O controller has 256 MB/s of bandwidth that the four parallel ports share. Each parallel port, if sending data from the memory to the I/O subsystem, has a maximum bandwidth of 135 MB/s. If the parallel port is sending data from the I/O subsystem to the memory, it has a maximum bandwidth of 88 MB/s.