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# Clock skew

## In circuit design

In circuit design, clock skew (sometimes timing skew) is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times. This can be caused by many different things, such as wire-interconnect length, temperature variations, variation in intermediate devices, capacitive coupling, material imperfections, and differences in input capacitance on the clock inputs of devices using the clock. As the clock rate of a circuit increases, timing becomes more critical and less variation can be tolerated if the circuit is to function properly.

### Harmful skew

There are two types of clock skew: negative skew and positive skew. Positive skew occurs when the clock reaches the receiving register later than it reaches the register sending data to the receiving register. Negative skew is the opposite: the receiving register gets the clock earlier than the sending register.

Two types of violation can be caused by clock skew. One problem is caused when the clock travels more slowly than the path from one register to another - allowing data to penetrate two registers in the same clock tick, or maybe destroying the integrity of the latched data. This is called a hold violation because the previous data is not held long enough at the destination flip-flop to be properly clocked through. Another problem is caused if the destination flip-flop receives the clock tick earlier than the source flip-flop - the data signal has that much less time to reach the destination flip-flop before the next clock tick. If it fails to do so, a setup violation occurs, so-called because the new data was not set up and stable before the next clock tick arrived. A hold violation is more serious than a setup violation because it cannot be fixed by increasing the clock period. Positive skew and negative skew cannot negatively impact setup and hold timing constraints respectively (see inequalities below).

### Beneficial skew

Clock skew can also benefit a circuit by decreasing the clock period at which the circuit will operate correctly. For each source register and destination register connected by a path, the following inequalities must hold:

1. $T ge reg + path_\left\{max\right\} + S - \left(s_d - s_s\right)$
2. $\left(s_d - s_s\right) le reg + path_\left\{min\right\} - H$

where

• T is the clock period,
• reg is the source register's clock to Q delay,
• $path_\left\{max\right\}$ is the path with the longest delay from source to destination,
• S is the setup time of the destination register
• $path_\left\{min\right\}$ is the path with the shortest delay from source to destination,
• H is the hold time of the destination register,
• $\left(s_d - s_s\right)$ represents the clock skew from the source to the destination registers,
• $s_d$ is the clock skew to the destination register, and
• $s_s$ is the clock skew to the source register.

## On a network

On a network such as the internet, clock skew describes the difference in time shown by the clocks at the different nodes on the network. It is usually an unavoidable phenomenon (at least if one looks at milli-second resolutions), but clock skew of tens of minutes or more is also quite common. A number of protocols (e.g. Network Time Protocol) have been designed to reduce clock skew, and produce more stable functions.

## References

• Friedman, E.G., ed., Clock Distribution Networks in VLSI Circuits and Systems, IEEE Press, 1995.
• Maheshwari, N., and Sapatnekar, S.S., Timing Analysis and Optimization of Sequential Circuits, Kluwer, 1999.
• Tam, S., Limaye, D.L., and Desai, U.N., "Clock Generation and Distribution for the 130-nm Itanium 2 Processor with 6-MB On-Die L3 Cache", in IEEE Journal of Solid-State Circuits, Vol. 39, No. 4, April 2004.