Two types of violation can be caused by clock skew. One problem is caused when the clock travels more slowly than the path from one register to another - allowing data to penetrate two registers in the same clock tick, or maybe destroying the integrity of the latched data. This is called a hold violation because the previous data is not held long enough at the destination flip-flop to be properly clocked through. Another problem is caused if the destination flip-flop receives the clock tick earlier than the source flip-flop - the data signal has that much less time to reach the destination flip-flop before the next clock tick. If it fails to do so, a setup violation occurs, so-called because the new data was not set up and stable before the next clock tick arrived. A hold violation is more serious than a setup violation because it cannot be fixed by increasing the clock period. Positive skew and negative skew cannot negatively impact setup and hold timing constraints respectively (see inequalities below).
On a network such as the internet, clock skew describes the difference in time shown by the clocks at the different nodes on the network. It is usually an unavoidable phenomenon (at least if one looks at milli-second resolutions), but clock skew of tens of minutes or more is also quite common. A number of protocols (e.g. Network Time Protocol) have been designed to reduce clock skew, and produce more stable functions.
Agency Reviews Patent Application Approval Request for "Estimation Apparatus and Method for Estimating Clock Skew"
Nov 14, 2013; By a News Reporter-Staff News Editor at Politics & Government Week -- A patent application by the inventors Chen, Ying-Yen...
Don't get skewed on your next ASIC design. (application-specific integrated circuit)(includes a related article on avoiding chip-to-chip clock skew) (clock skew problems)
Sep 02, 1991; You can minimize clock skew in large ASICs by considering its effects early in the design. Ignoring clock skew can cause costly...